Mpc System Bus; Processors; Processor Type Identification; Processor Pll Configuration - Motorola MTX Series Programmer's Reference Manual

MPC System Bus

Memory maps for the MTX are described in the following sections.

Processors

The processors supported are: 603e, 603ev, 604, and 604e. Parity checking
is not supported for the system address and data buses (that is, the Raven
and Falcon ASICs do not generate parity and do not check for parity on the
system address and data busses).

Processor Type Identification

The type of the processor can be determined by reading the Processor
Version Register (PVR). The following table shows the PVR values for the
supported processors:
Processor
603e (Stretch)
603ev (Valiant)
604
604e (Sirocco)
604e (Mach5)

Processor PLL Configuration

The processor internal clock frequency (Core Frequency) is multiple of the
system bus frequency. Each processor has four configuration pins,
PLL_CFG, for hardware strapping of the processor core frequency.

Look-Aside Cache

The look-aside external cache, when present, is implemented with the
Glance devices. Two Glance devices operate together to provide 256KB of
look-aside cache. The Glance devices are controlled via the System
External Cache Control Register (SXCCR).
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Table 1-11. PVR Values

PVR Value
0006 XXXXh
0007 XXXXh
0004 XXXXh
0009 XXXXh
000A XXXXh
Programming Model
1-13
1