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(9) Serial clock control circuit
The serial clock control circuit controls the serial clock to be supplied to the shift register, or controls the
clock to be output to the SCK pin when the internal system clock is used.
(10) Busy/acknowledge output circuit and bus release/command/acknowledge detection circuit
The busy/acknowledge output circuit and bus release/command/acknowledge detection circuit output and
detect control signals generated in the SBI mode.
These circuits do not operate in the three-wire or two-wire serial I/O mode.
(11) P01 output latch
The P01 output latch generates serial clock by software after the eighth serial clock has been output.
When the RESET signal is entered, this latch is set to 1.
To select the internal system clock as the serial clock, set the P01 output latch to 1.
5.6.3 Register Functions
(1) Serial operation mode register (CSIM)
Figure 5-40 shows the format of serial operation mode register (CSIM).
CSIM is an 8-bit register which specifies a serial interface operation mode, serial clock, wake-up function,
and so forth.
CSIM is manipulated using an 8-bit memory manipulation instruction. The higher three bits can be
manipulated bit by bit. Each bit can be manipulated using its name.
Each bit may or may not allow read and/or write operation (see Figure 5-40). Bit 6 allows bit test operation
only; any data written to this bit is invalid.
When the RESET signal is generated, all bits are cleared to 0.
Figure 5-40. Format of Serial Operation Mode Register (CSIM) (1/4)
Address
7
FE0H
CSIE
Remarks 1. (R) : Read only
2. (W): Write only
6
5
4
COI
WUP
CSIM4
Serial interface operation enable/disable specification bit (W)
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
3
2
1
CSIM3
CSIM2
CSIM1
Wake-up function specification bit (W)
Signal from address comparator (R)
Symbol
0
CSIM0
CSIM
Serial clock selection bit (W)
Serial interface operation mode selection bit (W)
127
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