Serial Clock Selection And Application (In The Sbi Mode) - NEC PD750004 User Manual

µPD750008 USER'S MANUAL
Bus release trigger bit (W)
RELT Control bit for bus release signal (REL) trigger output.
By setting RELT = 1, the SO latch is set to 1. Then the RELT bit automatically cleared to 0.
Caution Never clear SB0 (or SB1) during serial transfer. Be sure to clear SB0 (or SB1) before or
after serial transfer.
(4) Serial clock selection
To select the serial clock, manipulate bits 0 and 1 of serial operation mode register (CSIM). The serial
clock can be selected out of the following four clocks:
Table 5-9. Serial Clock Selection and Application (In the SBI Mode)
Mode register
CSIM CSIM
1 0
0 0 External
SCK
0 1 TOUT
flip-flop
0 f
1
X
1 1 f
X
When the internal system clock is selected, SCK is internally terminated when the 8th clock has been
output, and is externally counted until the slave enters the ready state.
(5) Signals
Figures 5-60 to 5-65 show signals to be generated in the SBI mode and flag operations on the SBIC. Table
5-10 lists signals used in the SBI mode.
160
Serial clock
Masking of
Source
serial clock
Automatically
masked when
8-bit data
transfer is
completed
4
/2
3
/2
Timing for shift register R/W and
start of serial transfer
<1> In the operation halt mode
(CSIE = 0)
<2> When the serial clock is
masked after 8-bit transfer
<3> When SCK is high
Application
Slave CPU
Arbitrary-speed
serial transfer
Middle-speed
serial transfer
High-speed
serial transfer