Figure 6-4. Configurations of the INT0, INT1, and INT4 Circuits
(a) Configuration of the INT0 circuit
INT0/P10
Noise eliminator
Selector
(b) Configuration of the INT1 circuit
INT1/P11
Input buffer
(c) Configuration of the INT4 circuit
INT4/P00
Input buffer
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X
Input buffer
Internal bus
Edge detection circuit
IM10
Detection edge specification
IM1
4
Internal bus
Both-edge
detection circuit
Internal bus
Edge detection
circuit
IM02
IM00, IM01
IM03
Detection edge
IM0
specification
Sampling clock selection
4
INT0
IRQ0
set signal
INT1
IRQ1
set signal
INT4
IRQ4
set signal
191