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µPD750008 USER'S MANUAL
Figure 5-33. Timer/Event Counter Mode Register Setup (2/2)
Address
FA8H
(b) Timer/event counter output enable flag (TOEn)
The TOEn is manipulated by a bit manipulation instruction.
The TOEn is cleared to 0 by an internal reset signal.
Figure 5-34. Timer/Event Counter Output Enable Flag Setup
Address
FA2H
FAAH
116
(b) In the case of timer counter (channel 1)
7
6
5
TM16
TM15
TM14
Count pulse (CP) selection bit
TM16
TM15
TM14
1
0
1
0
1
1
1
1
Other than above
Timer start indication bit
TM13
When "1" is written to the bit, the counter and IRQT1 flag are cleared.
If bit 2 is set to "1", count operation is started.
Operation mode
TM12
0
Stop (retention of count contents)
1
Count operation
TOE0
Channel 0
TOE1
Channel 1
4
3
2
1
TM13
TM12
Count pulse (CP)
12
0
f
/2
X
1
10
f
/2
X
8
0
f
/2
X
1
6
f
/2
X
Not to be set
Count operation
Timer/event counter output enable flag (W)
0
Disabled (outputs the low-level signal).
1
Enabled.
0
Symbol
TM1
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