NEC PD750004 User Manual page 141

(3) Error in reading the count register
The contents of the count register can be read using an 8-bit data memory manipulation instruction at
any time. During operation by such an instruction, all count pulse changes are held not to change the
count register. This means that if the count pulse signal source is applied to the TI0 input, as many count
pulses as corresponding to the time required to execute the instruction are cut. (When an internal clock
is used for the count pulse signal, this problem does not occur because of synchronization with the
instruction.)
Accordingly, in an attempt to read the contents of the count register with a count pulse signal applied to
TI0, the signal must have a pulse wide enough to avoid incorrect counting even if count pulses are cut.
That is, the contents of the count register are held by a read instruction for one machine cycle, so that
a signal applied to the TI0 pin must have a pulse wider than that.
External clock (TI0)
Instruction
CP
Count register
(4) Notes on changing the count pulse
When the count pulse is changed by rewriting the contents of the timer/event counter mode register, this
takes effect immediately after the rewrite instruction is executed.
Clock A
Clock B
CP
A combination of clocks used for changing count pulse signals can generate a spike (<1> or <2>) count
pulse as shown in the figure below. In this case, an incorrect count operation may occur, or the contents
of the count register may be destroyed. So when the count pulse is changed, bit 3 of the timer/event counter
mode register must be set to 1, and the timer must be restarted at the same time.
K – 1 K
A change in a count
pulse is placed on hold
by the instruction.
Re-set instruction
Clock A specified Clock B specified
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
Read instruction
K + 1
A count pulse is canceled
by the instruction.
Re-set instruction
Clock A specified
K + 2
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