Figure 5-4. Configurations of Ports 3n and 6n (n = 0 to 3)
Output latch
Corresponding bits of
port mode register group A
Note For port 6n only
PMmn = 0
Input buffer
M
P
PMmn = 1
X
PMmn
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
Note
Key interrupt
Input buffer with
hysteresis
Output buffer
m = 3, 6
n = 0 to 3
V
DD
Note
Bit m of
P-ch
POGA
Pull-up
resistor
Pmn
71