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Figure 5-40. Format of Serial Operation Mode Register (CSIM) (3/4)
Serial interface operation mode selection bit (W)
CSIM4
CSIM3
CSIM2
x
0
0
1
0
1
0
1
0
1
1
1
Remark x: Don't care
Serial clock selection bit (W)
CSIM1
CSIM0
3-wire serial I/O mode
0
0
Input clock externally applied to SCK pin
0
1
Timer/event counter output (TOUT0)
4
1
0
f
/2
X
3
1
1
f
/2
X
Remarks 1. Each mode can be selected using CSIE, CSIM3, and CSIM2.
Operation
Bit order of
mode
shift register
3-wire
SIO
7-0
serial
(Transfer start
I/O mode
with MSB)
SIO
0-7
(Transfer starting
with LSB)
SBI mode
SIO
7-0
(Transfer starting
with MSB)
2-wire
SIO
7-0
serial
(Transfer starting
I/O mode
with MSB)
(375 kHz: at 6.00 MHz,
262 kHz: at 4.19 MHz)
(750 kHz: at 6.00 MHz,
524 kHz: at 4.19 MHz)
CSIE
CSIM3
0
x
1
0
1
1
1
1
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
function
<—> XA
SO/P02
(CMOS output)
<—> XA
<—> XA
SB0/P02
(N-ch open-drain I/O)
P02 input
<—> XA
SB0/P02
(N-ch open-drain I/O)
P02 input
Serial clock
SBI mode
2-wire serial I/O mode
6
f
/2
(93.8 kHz: at 6.00 MHz,
X
65.47 kHz: at 4.19 MHz)
CSIM2
Operation mode
x
Operation halt mode
x
Three-wire serial I/O mode
0
SBI mode
1
Two-wire serial I/O mode
SO pin
SI/P03
(Input)
P03 input
SB1/P03
(N-ch open-drain I/O)
P03 input
SB1/P03
(N-ch open-drain I/O)
SI pin
function
SCK pin mode
Input
Output
129
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