Table of Contents
Advertisement
µPD750008 USER'S MANUAL
Figure 5-30. Timer/Event Counter Mode Register (Channel 0) Format
Address
FA0H
112
7
6
5
4
TM06
TM05
TM04
Count pulse (CP) selection bit
When f
= 6.00 MHz
X
TM06
TM05
TM04
0
0
0
0
0
1
1
0
0
1
0
1
1
1
0
1
1
1
Other than above
When f
= 4.19 MHz
X
TM06
TM05
TM04
0
0
0
0
0
1
1
0
0
1
0
1
1
1
0
1
1
1
Other than above
Timer start indication bit
TM03
When 1 is written into the bit, the counter and IRQT0 flag are cleared.
If bit 2 is set to 1, count operation is started.
Operation mode
TM02
0
Stop (retention of count contents)
1
Count operation
3
2
1
0
TM03
TM02
Count pulse (CP)
TI0 rising edge
TI0 falling edge
10
f
/2
(5.86 kHz)
X
8
f
/2
(23.4 kHz)
X
6
f
/2
(93.8 kHz)
X
4
f
/2
(375 kHz)
X
Not to be set
Count pulse (CP)
TI0 rising edge
TI0 falling edge
10
f
/2
(4.09 kHz)
X
8
f
/2
(16.4 kHz)
X
6
f
/2
(65.5 kHz)
X
4
f
/2
(262 kHz)
X
Not to be set
Count operation
Symbol
TM0
Advertisement
Table of Contents
