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Figure 5-2. Configurations of Ports 0 and 1
SI
Selector
8
CSIM
Input buffer
Input buffer
TI0
INT2 INT1 INT0
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
SCK
INT4
SO
P01
output
latch
Selector
Output buffer which can
N-ch
be switched to either
open drain
push-pull output or N-ch
open-drain output
Bit 1 of
POGA
or f
/64
X
Noise
eliminator
Input buffer with hysteresis
Internal
SCK
Pull-up
resistor
Bit 0 of
POGA
V
DD
Pull-up
resistor
V
DD
P-ch
P00/INT4
P01/SCK
P02/SO/SB0
P03/SI/SB1
P-ch
P10/INT0
P11/INT1
P12/INT2
P13/ TI0
69
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