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(a) Serial operation mode register (CSIM)
To use the two-wire serial I/O mode, set CSIM as shown below. (For details on CSIM format, see
(1) in Section 5.6.3.)
CSIM is manipulated using an 8-bit manipulation instruction. Bits 7, 6, and 5 of CSIM can be
manipulated bit by bit.
When the RESET signal is input, CSIM is set to 00H.
In the figure below, hatched portions indicate the bits used in the two-wire serial I/O mode.
Address
FE0H
Remark (R:
Read only
(W): Write only
Serial interface operation enable/disable specification bit (W)
Shift register operation
CSIE
1
Shift operation enabled
Signal from address comparator (R)
Note
COI
When the slave address register (SVA)
does not match the data of the shift register
Note COI can be read only before serial transfer is started or after serial transfer is completed. An
undefined value may be read during transfer. COI data written by an 8-bit manipulation instruction
is ignored.
Wake-up function specification bit (W)
WUP
0
Sets IRQCSI each time serial transfer is completed.
7
6
5
4
CSIE
COI
WUP CSIM4 CSIM3 CSIM2 CSIM1 CSIM0
Serial interface operation enable/disable specification bit (W)
Condition for being cleared (COI = 0)
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
3
2
1
Serial interface operation mode selection bit (W)
Wake-up function specification bit (W)
Match signal from address comparator (R)
Serial clock counter IRQCSI flag
Count operation
0
CSIM
Serial clock selection bit (W)
SO/SB0 and SI/SB1 pins
Can be set
Used in each mode
as well as for port 0
Condition for being set (COI = 1)
When the slave address register (SVA)
matches the data of the shift register
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