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Hardware
Processor clock control register
Clock
generator,
(PCC)
clock
System clock control register
output
(SCC)
circuit
Clock output mode register
(CLOM)
Sub-oscillator control register (SOS)
Interrupt request flag (IRQxxx)
Interrupt
Interrupt enable flag (IExxx)
Priority selection register (IPS)
INT0, INT1 and INT2 mode
registers (IM0, IM1, IM2)
Digital
Output buffer
ports
Output latch
I/O mode registers (PMGA,
PMGB, PMGC)
Pull-up resistor specification
register (POGA, POGB)
Bit sequential buffers (BSB0 to BSB3)
Table 8-1. Statuses of the Hardware after a Reset (2/2)
Generation of a RESET
signal in a standby mode
0
0
0
0
Reset (0)
0
0
0, 0, 0
Off
Clear (0)
0
0
Held
CHAPTER 8 RESET FUNCTION
Generation of a RESET
signal during operation
0
0
0
0
Reset (0)
0
0
0, 0, 0
Off
Clear (0)
0
0
Undefined
227
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