Sub-Oscillator Control Register (Sos) Format - NEC PD750004 User Manual

4 bit single-chip microcomputer
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(6) Sub-oscillator control register (SOS)
The SOS register specifies whether to use the built-in feedback register and controls the drive current
of the built-in inverter. (See Figure 5-18.)
Inputting a RESET signal clears all bits of the SOS register. The functions of each flag in the SOS register
are described below.
(a) SOS.0 (feedback resistor cut flag)
To use the feedback resistor of the subsystem clock, the mask option setup and switching SOS.0 by
software are required. Set SOS.0 to 0 to turn on the feedback circuit.
When the resonator is not used, set SOS.0 to 1. The feedback circuit is turned off, reducing the current
drain.
To use the resonator, be sure to select "Enable the feedback resistor" upon setting the mask option.
Then, set SOS.0 to 0 (feedback circuit is turned on).
(b) SOS.1 (drive capability switch flag)
The built-in inverter in the subsystem clock oscillator of the µPD750008 subseries has a large drive
current because it can be used at low supply voltage (V
too high to use at high supply voltage (V
so as to reduce the drive current of the inverter.
However, if SOS.1 is set to 1 when V
drive current. Set this flag to 0 when V
Figure 5-18. Sub-Oscillator Control Register (SOS) Format
Address
FCFH
Remark If the subsystem clock is not required , the XT1 and XT2 pins and SOS register must be
treated as follows:
XT1 : Connected to V
XT2 : Open
SOS: 0001B
DD
3
2
1
0
0
0
SOS1 SOS0
or V
.
SS
DD
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
= 1.8 V), so that the supply current becomes
DD
• 2.7 V). To reduce the supply current, set SOS.1 to 1
DD
is less than 2.7 V, the oscillation may stop for insufficient
is less than 2.7 V.
DD
Symbol
SOS
Cut flag for feedback resistor of the sub-oscillator
0
Built-in feedback resistor is used.
1
Built-in feedback resistor is not used.
Cut flag for the sub-oscillator current
0
Drive current is high (1.8 V
1
Drive current is low (2.7 V
Bits 2 and 3 of SOS must be set to 0.
V
)
DD
V
)
DD
*
93

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