Sck/P01 Pin Circuit Configuration - NEC PD750004 User Manual

µPD750008 USER'S MANUAL
Example To output one SCK/P01 pin clock cycle by software
SEL
MOV
MOV
CLR1 0FF0H.1
SET1 0FF0H.1
P01/SCK
The P01 output latch is mapped to bit 1 of address FF0H. A RESET signal sets the P01 output latch to
1.
Cautions 1. During normal serial transfer, the P01 output latch must be set to 1.
2. The P01 output latch cannot be addressed by specifying PORT0.1 (as described
below). The address of the latch (0FF0H.1) must be coded in the operand of an
instruction directly. However, MBE = 0 (or MBE = 1, MBS = 15) must be specified
before the instruction is executed.
CLR1
SET1
CLR1
SET1
180
MB15 ; or CLR1 MBE
XA,#10000011B ; SCK (f
CSIM,XA
; SCK/P01 <- 0
; SCK/P01 <- 1
Figure 5-80. SCK/P01 Pin Circuit Configuration
SCK pin output mode
PORT0.1
Not allowed
PORT0.1
0FF0H.1
Allowed
0FF0H.1
/2 3 ), output mode
X
Address
FF0H.1
P01
To internal circuit
output
latch
From the serial clock
control circuit
SCK