I/O Timing Of Digital I/O Ports; Pull-Up Resistor Specification Register Format; I/O Timing Chart Of Digital I/O Ports - NEC PD750004 User Manual

µPD750008 USER'S MANUAL
Pull-up resistor specification register group A
Address
FDCH
Pull-up resistor specification register group B
Address
FDEH

5.1.6 I/O Timing of Digital I/O Ports

Figure 5-9 shows the timing of data output to an output latch and the timing of taking in pin data or output
latch data on the internal bus.
Figure 5-10 shows an ON timing chart when a built-in pull-up resistor is connected to a port pin by software.
(a) When data is input by a 1-machine cycle instruction
Instruction
execution
Input timing
82
Figure 5-8. Pull-Up Resistor Specification Register Format
0
1
7 6 5
PO7 PO6 —
7 6 5
— —
—
Figure 5-9. I/O Timing Chart of Digital I/O Ports (1/2)
1 machine cycle
Manipulation instruction
Specification contents
Built-in pull-up resistor not connected
Built-in pull-up resistor connected
4 3 2
— PO3 PO2
4 3 2
—
— —
Symbol
1 0
PO1 PO0 POGA
Port 0 (P01 - P03)
Port 1 (P10 - P13)
Port 2 (P20 - P23)
Port 3 (P30 - P33)
Port 6 (P60 - P63)
Port 7 (P70 - P73)
Symbol
1 0
—
PO8 POGB
Port 8 (P80, P81)