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(1) Timer/event counter mode register (TM0, TM1)
The mode register (TMn) is an 8-bit register which controls the timer/event counter.
Its format is shown in Figures 5-30 and 5-31.
The timer/event counter mode register is set by an 8-bit memory manipulation instruction.
Bit 3 is a timer start bit and can be operated bit-wise. It is automatically reset to 0 when the timer operation
starts.
All the bits of the timer/event counter mode register are cleared to 0 by a RESET signal generation.
Examples 1. Start the timer in the interval timer mode of CP = 5.86 kHz (during 6.00 MHz operation).
SEL
MOV
MOV
2. Restart the timer according to the setting of the timer/event counter mode register.
SEL
SET1
MB15
; or CLR1 MBE
XA, #01001100B
TMn, XA
; TMn <– 4CH
MB15
; or CLR1 MBE
TMn.3
; TMn.bit3 <– 1
CHAPTER 5 PERIPHERAL HARDWARE FUNCTIONS
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