System Write Protection; Cp6005(X)-Sa-Specific Registers; Write Protection Register (Wprot) - Kontron CP6005-SA User Manual

6u compactpci processor board
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3 . 2 S y s te m Wr i te P ro t e c t i o n
The CP6005(X)-SA provides write protection for non-volatile memories via the DIP switch SW1, the uEFI
Shell and a backplane pin. If one of these sources is enabled, the system is write protected. Please con-
tact Kontron for further information before using these functions.
3 . 3 C P 6 0 0 5 ( X ) - S A - S p e c i f i c Re g i s te r s
Table 31: CP6005(X)-SA-Specific Registers
ADDRESS
0x284
0x285
0x288
0x28A
0x28C
0x28D
0x290
0x291
0x292
0x293
3.3.1 Wr ite Protection Register (WPROT)
The Write Protection Register holds the write protect signals for non-volatile devices.
Table 32: Write Protection Register (WPROT)
ADDRESS
BIT
7
NAME
SWP
ACCESS
R
RESET
0
BITFIELD
7
SWP
System write protection status:
0 = Onboard non-volatile memory devices not write protected
1 = Onboard non-volatile memory devices wr ite protected
3
SFWP
Reser ved
2
DSWP
This bit reflects the state of the system write protection via DIP switch SW1, switch 3:
0 = System not write protected via DIP switch
1 = System wr ite protected
1
BSWP
This bit reflects the state of the system write protection via backplane (SYS_WP#):
0 = System not write protected via backplane
1 = System wr ite protected
0
SSWP
This bit reflects the state of the system write protection via sof tware:
0 = System devices not write protected via sof tware
1 = System wr ite protected
If this bit is programmed once, it cannot be reprogrammed.
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Write Protection Register (WPROT)

Reset Status Register (RSTAT)
Board ID High Byte Register (BIDH)
Geographic Addressing Register (GEOAD)
Watchdog Timer Control Register (WTIM)
Board ID Low Byte Register (BIDL)
LED Conf iguration Register (LCFG)
LED Control Register (LCTRL)
General Purpose Output Register (GPOUT)
General Purpose Input Register (GPIN)
6
5
Reserved
R
000
DEVICE
0x284
4
3
2
SFWP
DSWP
R/W
R
0
0
DESCRIPTION
User Guide
CP6005(X)-SA
1
0
BSWP
SSWP
R
R/W
0
0
47

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