High-Speed Serial Rear I/O Interconnection; High-Speed Serial Rear I/O Interconnection Port Mapping - Kontron CP6005-SA User Manual

2.7.11 High-Speed Ser ial Rear I/O Interconnection
The high-speed serial rear I/O interconnection has been designed to meet the PICMG 2.20 R1.0 stan-
dard. In addition, Kontron has made minor improvements to ensure maximum signal integrity, such as:
» upgraded high-speed ZDplus connector mechanically compliant with the PICMG 2.20 provid-
ing better shielding to support up to 15 GHz signal frequency
» high-speed interconnection supporting 10GBASE-KR/40GBASE-KR4, one x8 PCI Express 3.0
port operating at 8 GT/s and two SATA 6 Gb/s ports
Note:
The PICMG 2.20 configuration allows coexistence with PICMG 2.16 fabrics.
Table 28: High-Speed Serial Rear I/O Interconnection Port Mapping
CON
J41
J4
www.kontron.com
POS PICMG 2.20
1 AUX
2 PORT 1
3 PORT 2
4 PORT 3
5 PORT 4
6 PORT 5
7 PORT 6
8 PORT 7
9 PORT 8
10 PORT 9
11 PORT 10
12 PORT 11
13 PORT 12
14 PORT 13
15 PORT 14
16 PORT 15
17 PORT 16
18 PORT 17
19 PORT 18
20 CLOCK
CP6005(X)-SA
PORT DEFINITION
PCIe Control PCIe Control
10GBASE-KR/ 10GBE1
40GBASE-KR4 Por t 1
--
--
--
10GBASE-KR/ 10GBE2
40GBASE-KR4 Por t 2
--
--
--
SATA 6 Gb/s Port 1 --
SATA 6 Gb/s Port 2 --
1 x8 PCIe --
Gen 3
--
--
--
1 x4 PCIe
Gen 2
PCIe Reference Clock PCIe Reference Clock
User Guide
CP6005X-SA
45