APPENDICES
No.
Name
No.1 CPU MULTR
SM528
complete
No.2 CPU MULTR
SM529
complete
No.3 CPU MULTR
SM530
complete
No.4 CPU MULTR
SM531
complete
Clock data read
SM801
request
(Note-1) : It is used for interlock condition of Multiple CPU high speed bus dedicated instruction when a synchronous system
set in Multiple CPU synchronous startup setting of system setting.
(Note-2) : The CPU No.1 is reset after the factor of the stop error is removed to cancel a stop error → Resetting is cancelled.
Table 1.1 Special relay list (Continued)
Meaning
OFF to ON :
• Turn ON when the data read from CPU No.1 is normal by
CPU No.1 read completion
OFF to ON :
• Turn ON when the data read from CPU No.2 is normal by
CPU No.2 read completion
OFF to ON :
• Turn ON when the data read from CPU No.3 is normal by
CPU No.3 read completion
OFF to ON :
• Turn ON when the data read from CPU No.4 is normal by
CPU No.4 read completion
OFF : Ignored
• When this relay is ON, clock data is read to SD210 to
ON : Read request
Details
MULTR instruction.
MULTR instruction.
MULTR instruction.
MULTR instruction.
SD213 as BCD values.
APP - 4
Set by
Remark
(When set)
S (Read completion)
U