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Panasonic Semiconductor Development Company
3.3
CPU Control Register
CPUM: CPU Mode Control Register
Bit:
15
14
13
12
NW
—
—
—
DEN
Reset:
1
0
0
0
R/W:
R/W
R
R
R
This register controls the invoking of all of the CPU modes.
NWDEN: Watchdog timer reset
0: Enable watchdog timer
1: Disable and clear watchdog timer
Setting the watchdog timer to 1, then setting it to 0 clears and restarts the
watchdog timer.
OSCID: Oscillator select
System clock monitor
0: Fast
1: Slow
STOP: STOP mode request
CPU operating state control. See table 3-2.
HALT: HALT mode request
CPU operating state control. See table 3-2.
OSC[1:0]: Oscillator control
See table 3-2.
Table 3-2 CPU Mode Bit Settings
STOP HALT OSC1 OSC0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
x
Note: All unindicated bit settings are reserved.
76
Panasonic
11
10
9
8
7
6
—
—
—
—
—
—
0
0
0
0
0
0
R
R
R
R
R
R
CPU Mode
0
NORMAL
1
SLOW
HALT0 (Invoked
0
from NORMAL)
HALT1 (Invoked
1
from SLOW)
x
STOP
MN102H75K/F75K/85K/F85K LSI User Manual
Low-Power Modes
CPU Control Register
x'00FC00'
5
4
3
2
1
OSC
—
STOP HALT OSC1 OSC0
ID
0
0
0
0
0
R
R
R/W
R/W
R/W
Clock
System
to CPU
Clock
PLL CPU
24 MHz
12 MHz
On
4 MHz
2 MHz
Off
24 MHz
12 MHz
On
4 MHz
2 MHz
Off
Off
Off
Off
0
0
R/W
On
On
Off
Off
Off
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