Panasonic MN10285K User Manual page 49

The watchdog timer interrupt is
provided for detecting and handling
racing. Normal operation is not
guaranteed if the program returns
after a watchdog interrupt. For
actions requiring returns, use a
timer interrupt.
Panasonic Semiconductor Development Company
IAGR: Accepted Interrupt Group Number Register
Bit: 15 14 13 12
— — — —
Reset: 0 0 0 0
R/W: R R R R
IAGR returns the group number of an accepted interrupt, indicated in the
6-bit GN field. When the interrupt handler has to calculates the header
address for the interrupt service routine, it merely needs to add the contents
of IAGR to the header address for the table in which are registered the vec-
tor addresses for servicing all interrupts. IAGR is a 16-bit access register.
GN[5:0]: Group Number
Contains the group number multiplied by four.
EXTMD: External Interrupt Mode Register
Bit: 15 14 13 12
IQ5TG
— — — —
Reset: 0 0 0 0
R/W: R R R R R/W
EXTMD sets the trigger conditions for external interrupts. IQnTG[1:0]
sets the interrupt mode on the associated IRQ pin. Each IRQ pin can have
any polarity or edge setting. EXTMD is a 16-bit access register.
00: Active-low interrupt
01: Either-edge-triggered interrupt (positive or negative)
10: Negative-edge-triggered interrupt
11: Positive-edge-triggered interrupt
WDICR: Watchdog Interrupt Control Register
Bit: 7 6 5 4
— — — —
Reset: 0 0 0 0
R/W: R R R R
WDICR is an 8-bit access register.
WDID: Watchdog interrupt detect flag
0: Interrupt undetected
1: Interrupt detected
48
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11 10 9 8 7 6
— — — — GN5 GN4
0 0 0 0 0 0
R R R R R R
11 10 9 8 7 6
IQ5TG IQ4TG IQ4TG IQ3TG IQ3TG
1 0 1 0 1 0
0 0 0 0 0 0
R/W R/W R/W R/W R/W
3 2 1 0
— — — WDID
0 0 0 0
R R R R/W
MN102H75K/F75K/85K/F85K LSI User Manual
Interrupts
Interrupt Control Registers
x'00FC0E'
5 4 3 2 1
GN3 GN2 GN1 GN0 —
0 0 0 0 0
R R R R R
x'00FCF8'
5 4 3 2 1
IQ2TG IQ2TG IQ1TG IQ1TG IQ0TG IQ0TG
1 0 1 0 1
0 0 0 0 0
R/W R/W R/W R/W R/W R/W
x'00FC42'
0
—
0
R
0
0
0