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4.11.5 Setting Up a Two-Phase Capture Input Using Timer 4
In this example, timer 4 is used to divide the timer 0 underflow by 65,536 and
measure the number of cycles from the rising edge of the TM4IA input signal to
the rising edge of the TM4IB input signal. An interrupt occurs on capture B and
the software calculates the number of cycles by subtracting the contents of
TMnCA from the contents of TMnCB.
P3
P6
TM4IA
P2
TM4IB
Timer 4
Timer 0
underflow
up
TM4IA
Interrupt B
TM4IB
Figure 4-37 Block Diagram of Two-Phase Capture Input Using Timer 4
To set up timer 0:
1.
Disable timer 0 counting in the timer 0 mode register (TM0MD). This step is
unnecessary immediately after a reset, since TM0MD resets to 0.
TM0MD (example)
Bit:
7
6
5
4
TM0
TM0
—
—
EN
LD
Setting:
0
0
0
0
2.
Set the divide-by ratio for timer 0. To divide B
the timer 0 base register (TM0BR). (The valid range for TM0BR is 0 to
255.)
108
Panasonic
16-Bit Timer Setup Examples
CORE
ROM, RAM
Interrupts
Bus Controller
Timers 0-3
Serial I/Fs
Timers 4-5
ADC
A. Chip Level
TM4BC
TM4CA
T
R
S
TM4CB
T
B. Block Level
3
2
1
0
TM0
TM0
—
—
S1
S0
0
0
—
—
OSC
MN102H75K/F75K/85K/F85K LSI User Manual
Timers
P4
P5
Q
Q
Q
x'00FE20'
/4 by two, write x'01' to
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