Panasonic MN10285K User Manual page 110

Timers
16-Bit Timer Setup Examples
Do not change the clock source
once you select it. Selecting the
clock source while you set up
the count operation control will
corrupt the value in the binary
counter.
In the bank and linear address-
ing versions of the MN102
series, it was necessary to set
TM0EN and TM0LD to 0
between steps 3 and 4, to
ensure stable operation. This is
unnecessary in the high-speed
linear addressing version.
Use the MOV instruction for this
setup and only use 16-bit write
operations.
This step stops the TM4BC
count and clears both TM4BC
and the S-R flip-flop to 0.
When TM4MD[1:0] = b'11' (dur-
ing capture), TM4CA and
TM4CB become read-only regis-
ters. To write to TM4CA or
TM4CB, you must first set
TM4MD[1:0] = b'00'.
MN102H75K/F75K/85K/F85K LSI User Manual
TM0BR (example)
Bit: 7 6 5 4
TM0 TM0 TM0 TM0
BR7 BR6 BR5 BR4
Setting: 0 0 0 0
3. Set the TM0LD bit of the TM0MD register to 1. This loads the value in the
base register to the binary counter. At the same time, select the clock source
as B /4 by writing b'00' to TM0S[1:0].
OSC
TM0MD (example)
Bit: 7 6 5 4
TM0 TM0
— —
EN LD
Setting: 0 1 0 0
4. Set TM0LD to 0 and TM0EN to 1. This starts the timer. Counting begins at
the start of the next cycle. When the binary counter reaches 0 and loads the
value x'01' from the base register, in preparation for the next count, a timer 0
underflow interrupt request is sent to the CPU.
To set up timer 4:
1. Set the operating mode in the timer 4 mode register (TM4MD). Disable
timer 4 counting and interrupts. Select up counting. Set the TM4NLP bit to 0
to select looped counting from 0 to x'FFFF'. Select timer 0 underflow as the
clock source.
TM4MD (example)
Bit: 15 14 13 12
TM4 TM4 TM4
— —
EN NLD UD1
Setting: 0 0 0 0
2. Set the TM4NLD bit of the TM4MD register to 1 and the TM4EN bit to 0.
This enables TM4BC and the S-R flip-flop. This step ensures stable opera-
tion. If it is omitted, the binary counter may not count the first cycle. Do not
change any other operating modes during this step.
3. Set TM4NLD and TM4EN to 1. This starts the timer. Counting begins at the
start of the next cycle.
To enable timer 4 capture B interrupts:
Cancel all existing interrupt requests. Next, set the interrupt priority level in the
TM4CBLV[2:0] bits of the TM4CBICH register (levels 0 to 6), set the TM4BIE
bit to 1, and set the TM4BIR bit of TM4CBICL to 0. From this point on, an
interrupt request is generated whenever a timer 4 capture B event occurs.
109
Panasonic
3 2 1 0
TM0 TM0 TM0 TM0
BR3 BR2 BR1 BR0
0 0 0 1
3 2 1 0
TM0 TM0
— —
S1 S0
0 0 0 0
11 10 9 8 7 6
TM4 TM4 TM4 TM4 TM4
UD0 TGE ONE MD1 MD0
0 0 0 0 1 1
Panasonic Semiconductor Development Company
x'00FE10'
x'00FE20'
x'00FE80'
5 4 3 2 1
TM4 TM4 TM4 TM4 TM4 TM4
ECLR LP ASEL S2 S1
0 0 1 or 0 0 0
0
S0
0