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General Description
MN102H Series Description
CPU Core
Maskable Interrupt
Nonmaskable Interrupt
Receive
Interrupt Enable
Interrupt Masking
6
5
4
3
2
1
0
Note: Interrupt control hardware configuration varies between products.
MN102H75K/F75K/85K/F85K LSI User Manual
Interrupt controller
An interrupt controller external to the core controls all nonmaskable and
maskable interrupts except reset. There are a maximum of sixteen interrupt
classes (class 0 to 15). Each class can have up to four interrupt factors and any of
seven priority levels.
Reset
Receive
Receive
Figure 1-6 Interrupt Controller Configuration
The CPU checks the processor status word to determine whether or not to accept
an interrupt request. If it accepts the request, automatic hardware servicing
begins and the contents of the program counter and other necessary registers are
pushed to the stack. The program then looks up and branches to the entry address
of the interrupt service routine for the interrupt that occurred.
Main program
Hardware processing
Push PC, PSW
Interrupt
Max. 6 machine cycles
Figure 1-7 Interrupt Servicing Sequence
Panasonic
Interrupt Controller
Groups 0-3
Nonmaskable Interrupt Controllers
Nonmaskable Interrupt
Control Registers (NMICR)
(WDICR)
(UNICR)
Group 4
Maskable Interrupt Controllers
Maskable Interrupt
Control Registers (xx ICR)
Group 63
Maskable Interrupt Controllers
Maskable Interrupt
Control Registers (xx ICR)
Interrupt preprocessing
Push registers, branch to entry address, etc.
x'080008'
7 machine cycles
Panasonic Semiconductor Development Company
25
Reset
Nonmaskable interrupts
4
(
External NMI pin input
Watchdog timer
Undefined instruction
Interrupt occurred,
but no vector exists
(EIICR)
4
Maskable interrupts
Max. 240 vectors
(
External pin interrupts
4
Peripheral interupts
Interrupt service routine
Header resets interrupt vector
JMP, etc.
)
)
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