Interrupts; Description; Interrupt Controller Block Diagram; Panasonic - Panasonic MN10285K User Manual

Interrupts

Description

2 Interrupts
MN102H75K/F75K/85K/F85K LSI User Manual
2.1 Description
The most important factor in real-time control is an MCU's speed in servicing
interrupts. The MN102H75K/85K has an extremely fast interrupt response time
due to its ability to abort instructions, such as multiply or divide, that require
multiple clock cycles. The MN102H75K/85K re-executes an aborted instruction
after returning from the interrupt service routine.
This section describes the interrupt system in the MN102H75K/85K. The
MN102H75K/85K contains 36 interrupt group controllers. Each controls a single
interrupt group. Because each group contains only one interrupt vector, the
MN102H75K/85K can handle interrupts much quicker than previously possible.
Each interrupt group belongs to one of twelve classes, which defines its interrupt
priority level.
With the exception of reset interrupts, all interrupts from timers, other peripheral
circuits, and external pins must be registered in an interrupt group controller.
Once they are registered, interrupt requests are sent to the CPU in accordance
with the interrupt mask level (0 to 6) set in the interrupt group controller. Groups
1 to 3 are dedicated to system interrupts. Table 2-1 compares the interrupt
parameters of the MN102H75K/85K to those of the MN102L35G, the com-
parable MCU in the previous generation of the 16-bit series.
Table 2-1 Comparison of MN102H75K/85K and MN102L35G Interrupt Features
Parameter
Interrupt groups 4 vectors per group
(IAGR group numbers (Separated by interrupt
Interrupt response time
Interrupt level settings 4 vectors per level
Software compatibility
The MN102H75K/85K has six external interrupt pins. Set the interrupt condition
(positive edge, negative edge, either edge, or active low) in the EXTMD register.
.
.
Internal
.
interrupts
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
Figure 2-1 Interrupt Controller Block Diagram
37

Panasonic

MN102L35G MN102H75K/85K
1 vector per group
(Group number gener-
service routine)
ated for each interrupt)
Good Excellent
4 vectors per level
— Easily modified
.
.
.
EXTMD
Edge/level
Edge/level
Edge/level
Edge/level
Edge/level
Edge/level
Panasonic Semiconductor Development Company
Interrupt
to CPU
Interrupt
arbitration