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Panasonic Semiconductor Development Company
5.6.2
Setting Up Synchronous Serial Reception Using Serial
Interface 0
This example illustrates serial reception in the synchronous serial mode with the
following settings:
LSB first
8-bit character length
Odd parity
When a reception end interrupt occurs, the CPU reads the data byte.
To set up the input port:
Set the P5DIR7 bit of the port 5 I/O control register (P5DIR) to 0. This sets the
SBT0 pin to input.
To set up serial interface 0:
Configure the reception settings in the serial port 0 control register (SC0CTR).
Select timer 0 underflow x 1/8 as the serial port 0 clock source. Select timer 0
underflow x 1/8 as the serial port 0 clock source. Select synchronous serial mode,
odd parity, 8-bit data length, and LSB-first output.
SC0CTR (example)
Bit:
15
14
13
12
SC0
SC0
SC0
SC0
SC0
TEN
REN
BRE
I2CS
PTL
Setting:
1
1
0
0
To enable serial 0 transmission end interrupts:
Cancel all existing interrupt requests. Next, set the interrupt priority level of 5 in
the ANLV[2:0] bits of the ANICH register, set the SCR0IE bit of SCR0ICH to 1,
and set the SCR0IR bit of SCR0ICL to 0. From this point on, an interrupt request
is generated whenever a serial data reception ends.
ANICH: (example)
Bit:
7
6
5
4
—
ANLV2 ANLV1 ANLV0
Setting:
0
1
0
1
SCR0ICL (example)
Bit:
7
6
5
4
SCR0
—
—
—
IR
Setting:
0
0
0
0
SCR0ICH (example)
Bit:
7
6
5
4
—
—
—
—
Setting:
0
0
0
0
134
Panasonic
Serial Interface Setup Examples
11
10
9
8
7
6
SC0
SC0
SC0
SC0
—
OD
I2CM
LN
PTY2
1
0
0
0
1
1
3
2
1
0
—
—
—
ANIE
0
0
0
0
3
2
1
0
SCR0
—
—
—
ID
0
0
0
0
3
2
1
0
SCR0
—
—
—
IE
0
0
0
1
MN102H75K/F75K/85K/F85K LSI User Manual
Serial Interfaces
x'00FD80'
5
4
3
2
1
SC0
SC0
SC0
SC0
SC0
—
PTY1
PTY0
SB
S1
S0
1
1
0
0
0
x'00FC81'
x'00FC84'
x'00FC85'
0
1
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