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2
I
C Bus Controller
2
I
C Interface Setup Examples
Data
(slave address)
S
1
0
0
1
0
SDA
SCL
Note: The circled areas are signals output from the MN102H75K/85K.
Figure 13-8 Waveform for Slave Receiver Transitioning to Slave Transmitter
MN102H75K/F75K/85K/F85K LSI User Manual
13.6.2.3 Setting Up the Second Interrupt
The master sends an ACK = 0 signal, so the microcontroller must send the next
data byte. Set up the transmission data as follows:
To set up the interrupt:
Set the I2C0ICH and I2C0ICL register pair (x'00FC9C') to x'0100'. This
2
enables I
C interrupts and clears the previous interrupt request.
2
To set up the I
C registers:
1.
Read the I2CDREC register (x'007E42') to determine the I
status. The previous read from I2CDREC cleared the AAS, so AAS should
be 0.
2.
Set the I2CDTRM register (x'007E40') to x'01AA0'. This sets STA to 0,
STP to 0, ACK to 1, and the transmission data to x'AA'. The microcontroller
does not need to issue an ACK signal in this transfer, so the ACK bit should
be 1.
3.
Begin transmitting data in sync with the clock from the master.
13.6.2.4 Setting Up the Third Interrupt
The master send an ACK = 1 signal, then issues a stop condition, ending the
communication.
ACK
R/W
0
0
1
1
0
0
0
ACK
0
1
0
1
1
0
1
Panasonic Semiconductor Development Company
303
Panasonic
2
C bus controller
ACK
1
0
1
1
0
0
0
1
P
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