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Panasonic MN101C00 User Manual

Panaxseries mn101c00 series 8-bit single-chip microcomputers
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MICROCOMPUTER
MN101C00
MN101C115/117
LSI User's Manual
Pub. No. 21411-011E

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Summary of Contents for Panasonic MN101C00

  • Page 1 MICROCOMPUTER MN101C00 MN101C115/117 LSI User’s Manual Pub. No. 21411-011E...

  • Page 3: Contents

    PanaXSeries is a trademark of Matsushita Electric Industrial Co., Ltd. The other corporation names,logotype and product names written in this book are trademarks or registered trademarks of their corresponding corporations. Request for your special attention and precautions in using the technical information and semiconductors described in this book An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this book and controlled under the "Foreign Exchange and...

  • Page 4: Overview

    How to Read This Manual The MN101C11x incorporates more than one ROM/RAM to meet a variety of applications. An EPROM version as well as a Mask ROM version is available so users can write a program by themselves. Organization In this LSI manual, the MN101C117 functions are presented in the following order: overview, CPU basic functions, port functions, timer functions, serial functions, and other peripheral hardware functions.

  • Page 5: Precautions And Warnings

    Manual Configuration Each section of this manual consists of a title, summary, main text, supplemental information, precautions and warnings. The layout and definition of each section are shown below. Subtitle 4-3 16-bit Timer Operation (timer 4) Sub-subtitle The smallest block 4-3-1 Overview in this manual.
  • Page 6 Where to Send Inquires Please send any inquires or questions concerning the contents of this manual to the Panasonic semiconductor design center closest to you. A list of addresses is provided at the end of this manual for your convenience.

  • Page 7: Table Of Contents

    Contents Chapter 1 Overview Chapter 2 Basic CPU Functions Chapter 3 Port Functions Chapter 4 Timer Functions Chapter 5 Serial Functions A/D Conversion Chapter 6 Functions AC Zero-Cross Chapter 7 Circuit/Noise Filter Appendices...
  • Page 9 Contents...
  • Page 10 Contents Chapter 1 1-1 Product Overview...2 1-1-1 1-1-2 1-2 Hardware Functions ...3 1-3 Pins ...5 1-3-1 1-3-2 1-4 Overview of Functions ...12 1-4-1 1-5 Electrical Characteristics...13 1-5-1 1-5-2 1-5-3 1-5-4 1-6 Option...22 1-6-1 1-6-2 1-7 Outline Drawings ...24 Chapter 2 2-1 Overview ...28 2-2 Address Space 2-2-1...

  • Page 11: Port Functions

    Chapter 3 Port Functions 3-1 Overview ...38 3-2 Port Control Registers ...41 3-2-1 Overview ...41 3-2-2 I/O Port Control Registers ...45 3-3 I/O Port Configuration and Functions...47 Chapter 4 Timer Functions 4-1 Overview ...56 4-2 8-bit Timer Operation (timers 2, 3) ...62 4-2-1 Overview ...62 4-2-2...

  • Page 12: Serial Functions

    Chapter 5 Serial Functions 5-1 Overview ...92 5-2 Synchronous Serial Interface ...94 5-2-1 5-2-2 5-2-3 5-3 Half-duplex UART Serial Interface ...101 5-3-1 5-3-2 5-3-3 5-4 Serial Interface Control Registers ...106 5-4-1 5-4-2 5-4-3 5-4-4 Chapter 6 A/D Conversion Functions 6-1 Overview ...114 6-2 A/D Conversion...115 6-3 A/D Converter Control Registers ...117 6-3-1...
  • Page 13 Appendices 8-1 EPROM Versions ...130 8-1-1 Overview ...130 8-1-2 Cautions on Use...131 8-1-3 Erasing Written Data in Windowed Packages ...132 (PX-AP101C11-SDC, PX-AP101C11-FBC) 8-1-4 Characteristics of EPROM Versions...133 8-1-5 Writing to Internal EPROM...134 8-1-6 Cautions on Handling the ROM Writer...136 8-1-7 Option Bit ...137 8-1-8 Writing Adapter Connection...138...

  • Page 15: Overview

    Chapter 1 Overview...

  • Page 16: Product Overview

    1-1 Product Overview 1-1-1 Overview The MN101C00 series of 8-bit single-chip microcomputers incorporate several types of peripheral functions. This chip series is well suited for VCR, MD, TV, CD, LD, printer, telephone, home automation, pager, air conditioner, PPC, remote control, fax machine, musical instrument, and other applications.

  • Page 17: Hardware Functions

    1-2 Hardware Functions ROM/RAM Size: <Single chip mode> Internal ROM Internal RAM Machine Cycles: High speed mode 0.10µs/20MHz (4.5V to 5.5V) Low speed mode 125µs/32KHz(2.0V to 5.5V)* Interrupts: 12 interrupts(11 interrupts except for 48-pin QFH package) <External interrupts> The active edge can be selected for all external interrupts IRQ0 External interrupt (can be connected to noise filter) IRQ1 External interrupt (can determine zero crossings, can be connected to noise filter)
  • Page 18 Chapter 1 Overview 26 ports for 44-QFP 27 ports for 48-QFH 12 ports for 48-QFH 4 ports for 48-QFH Hardware Functions Timers 2 and 3 can be cascaded. Timer 4 Square wave output, 16-bit PWM output are possible. Clock source: fosc, fs/4, fs/16, TM4IO pin input Input capture function Time base timer Clock source: fosc, fs/4, fx*...

  • Page 19: Pins

    1-3 Pins 1-3-1 Pin Diagram TXD,SBO0,P00 RXD,SBI0,P01 SBT0,P02 BUZZER, P06 RMOUT,P10 TM2IO,P12 TM3IO,P13 TM4IO,P14 IRQ0,P20 IRQ1,P21 IRQ2,P22 NRST, P27 Figure 1-3-1 Pin Diagram (42-SDIP: TOP VIEW) Chapter 1 Overview OSC1 OSC2 PA7,AN7 PA6,AN6 PA5,AN5 PA4,AN4 PA3,AN3 PA2,AN2 PA1,AN1 PA0,AN0 P80,LED0 P81,LED1 P82,LED2 P83,LED3...
  • Page 20 Chapter 1 Overview LED3,P83 LED2,P82 LED1,P81 LED0,P80 AN0,PA0 AN1,PA1 AN2,PA2 AN3,PA3 AN4,PA4 AN5,PA5 AN6,PA6 Pins MN101C117/115 ４４-ＱＦＰ 12 13 14 15 16 17 18 19 20 21 22 Figure 1-3-2 Pin Diagram (44-QFP: TOP VIEW) P22,IRQ2 P21,IRQ1,SENS P20,IRQ0 P14,TM4IO P13,TM3IO P12,TM2IO...
  • Page 21 48 47 LED3,P83 LED2,P82 LED1,P81 LED0,P80 MN101C117/115 AN0,PA0 AN1,PA1 AN2,PA2 AN3,PA3 AN4,PA4 AN5,PA5 AN6,PA6 13 14 15 16 17 18 19 20 21 22 23 24 Figure 1-3-3 Pin Diagram (48-QFH: TOP VIEW) ４８-ＱＦＨ Chapter 1 Overview P23,IRQ3 P22,IRQ2 P21,IRQ1,SENS P20,IRQ0 P14,TM4IO P13,TM3IO...

  • Page 22: Pin Function Summary

    Chapter 1 Overview Pin No. Name Type Dual Function – OSC1 Input OSC2 Output Input Output 20 to 23 P00 to P02 I/O SBO0(TXD), I/O port 0 SBI0(RXD), SBT0, (BUZZER) Pins 1-3-2 Pin Function Summary *The pin numbers in the list correspond to the QFH package(Refer to Figure 1-3-3 Pin connection.) Be careful when using SDIP and QFP packages.
  • Page 23 Pin No. Name Type Dual Function 24 to 28 P10 to P14 RMOUT, TM2IO to TM4IO 29 to 32 P20 to P23 Input IRQ0, IRQ1(SENS), IRQ2 to 3 Input 33 to 40 P60 to P67 41 to 42 P70 to P71 I/O 1 to 4 P80 to P87 I/O LED0 to 7...
  • Page 24 Chapter 1 Overview Pin No. Name Type Dual Function Output SBO0(P00) Input SBI0(P01) SBO0 Output TXD(P00) SBI0 Input RXD(P01) SBT0 Buzzer RMOUT 26 to 28 TM2IO to P12 to P14 TM4IO Pins Table 1-3-1 Pin Function Summary (3/4) Function UART transmit In the serial interface in UART mode, these pins are configured as data output pin the receive data input pin and transmit data output pin.
  • Page 25 Pin No. Name Type Dual Function MMOD Input 29 to 32 IRQ0 to Input P20, IRQ3 P21(SENS), P22,P23 6 to 13 AN0 to AN7 Input PA0 to PA7 SENS Input IRQ1(P21) Table 1-3-1 Pin Function Summary (4/4) Function This pin sets the test mode. Test mode switch input pin Must be set to L.

  • Page 26: Overview Of Functions

    16 KB 8-bit timer 2 8-bit timer 3 16-bit timer 4 A/D conversion Figure 1-4-1 Block Diagram of Functions) MN101C00 512 bytes External interrupt Serial interface 0 Time base timer 5 Watchdog timer P80,LED0 P81,LED1 P82,LED2 P83,LED3...

  • Page 27: Electrical Characteristics

    1-5 Electrical Characteristics Model MN101C117/115 Contents Classification CMOS integrated circuit General purpose Function CMOS, 8-bit, single-chip microcomputer 1-5-1 Absolute Maximum Ratings Parameter Supply voltage Input clamp current (SENS) Input pin voltage Output pin voltage I/O pin voltage Peak output Except P8 current All pins Average output...

  • Page 28: Operating Conditions

    Chapter 1 Overview 700k MN101C The instruction cycle is twice the clock cycle. The feedback resistor is built-in. Figure 1-5-1 Crystal Oscillator 1 Electrical Characteristics 1-5-2 Operating Conditions Parameter Symbol Supply voltage Supply voltage 3 during operation 5 Voltage to maintain RAM data V Operating speed Instruction execution time tc4 *...
  • Page 29 Parameter Symbol External clock input 1 OSC1 (OSC2 is unconnected) 18 Clock frequency 19 High level pulse width twh 1 20 Low level pulse width twl 1 21 Rise time twr 1 22 Fall time twf 1 External clock input 2 XI (XO is unconnected)*2 23 Clock frequency 24 High level pulse width twh 2...
  • Page 30 Chapter 1 Overview twr1 Figure 1-5-3 OSC1 Timing Chart twr2 Figure 1-5-4 XI Timing Chart Electrical Characteristics twh1 twf1 twh2 twf2 twl1 twl2 0.9V 0.1V 0.9V 0.1V...

  • Page 31: Dc Characteristics

    1-5-3 DC Characteristics Parameter Symbol Supply current (no load at output) 1 Supply current 2 during operation Supply current during HALT mode Supply current during STOP mode Notes: Measured under conditions of Ta=25°C and no load. The supply current during operation, I following conditions: After all I/O pins are set to input mode and the oscillation is set to <NORMAL mode>, the MMOD pin is fixed at V fixed at V...
  • Page 32 Chapter 1 Overview Electrical Characteristics Parameter Symbol Input pin 1 MMOD 8 Input high voltage 1 9 Input high voltage 2 10 Input low voltage 1 11 Input low voltage 2 12 Input leakage current Input pin 2 P20, P22~P23 (Schmitt trigger input) 13 Input high voltage 14 Input low voltage 15 Input leakage current...
  • Page 33 SENS pin Rise time Fall time Input voltage level 1 (Input) Input voltage level 2 (Output) Figure 1-5-5 Operation of AC Zero-Cross Detection Circuit Parameter Symbol Input pin 4 PA0~PA7 29 Input high voltage 1 30 Input high voltage 2 31 Input low voltage 1 32 Input low voltage 2 33 Input leakage current...
  • Page 34 Chapter 1 Overview Parameter Symbol I/O pin 5 P27 (RST) 36 Input high voltage 37 Input low voltage 38 Input leakage current 39 Input high current I/O pin 6 P00 to P06, P10 to P14 (Schmitt trigger input) 40 Input high voltage 41 Input low voltage 42 Input leakage current 43 Input high current...

  • Page 35: A/D Converter Characteristics

    Parameter Symbol I/O pin 9 P80~P87 63 Input high voltage 1 IH13 64 Input high voltage 2 IH14 65 Input low voltage 1 IL113 66 Input low voltage 2 IL14 67 Input leakage current LK13 68 Input high current IH13 69 Output high voltage OH13 70 Output low voltage...

  • Page 36: Rom Option

    Chapter 1 Overview − Option 1-6 Option 1-6-1 ROM Option The product equipped with this LSI or an EPROM with this LSI controls the oscillation mode after resetting as well as the runaway-detection watchdog timer, using bits 2 to 0 of the last address of the built-in ROM. Option bits −...

  • Page 37: Option Check List

    1-6-2 Option Form Model MN101C Name 1. Oscillation mode Type B Type A Note: Type A: Operation begins from the reset cycle in the NORMAL mode. Type B: Operation begins from the reset cycle in the SLOW mode. 2. Watchdog timer period setting Selection Detection Period fs/2...

  • Page 38: Outline Drawings

    Chapter 1 Overview External Dimensions 1-7 Outline Drawings Body Material: Epoxy Resin Lead Material:Fe Ni Figure 1-7-1 42-SDIP The external dimensions of the package are subject to change. Before using this product, please obtain product specifications from the sales office. Package code: SDIP042-P-0600 Unit: mm Lead Finish Method:Soldering dip...
  • Page 39 Body Material: Epoxy Resin Figure 1-7-2 44-QFP The external dimensions of the package are subject to change. Before using this product, please obtain product specifications from the sales office. Package code: QFP044-P-1010 Lead Material:Fe Ni Lead Finish Method:Soldering dip External Dimensions) Chapter 1 Overview Unit: mm...
  • Page 40 Chapter 1 Overview Package code: QFH048-P-0707 Unit: mm Material: Epoxy Resin Lead Material:Fe Ni-42 Alloy Lead Finish Method:Soldering dip Figure 1-7-3 48-QFH The external dimensions of the package are subject to change. Before using this product, please obtain product specifications from the sales office.

  • Page 41: Basic Cpu Functions

    Chapter 2 Basic CPU Functions...

  • Page 42: Overview

    Chapter 2 Basic CPU Functions Overview/Address Space 2-1 Overview Basic CPU functions are in conformance with the MN101C00 series manual (architecture manual). This chapter describes specifications unique to the MN101C117/115. 2-2 Address Space 2-2-1 Memory Configuration X'00000' 256 bytes 512 bytes...

  • Page 43: Bus Interface

    2-2-2 Special Function Registers Memory control register(MEMCTR) is a 4-bit register which set up the base Table 2-2-1 Register Map 03F0X CPUM MEMCTR WDCTR DLYCTR 03F1X P0OUT P1OUT P2OUT P0IN P1IN P2IN 03F2X 03F3X P0DIR P1DIR 03F4X P0PLU P1PLU P2PLU SC0MD0 SC0MD1 SC0MD2 SC0MD3 SC0CTR SC0TRB SC0RXB...

  • Page 44: Overview

    Chapter 2 Basic CPU Functions IOW1 IOW0 MEMCTR Bus Interface 2-3 Bus Interface 2-3-1 Overview The MN101C117, unlike other MN101C series microcomputers, does not support memory expansion mode and processor mode. 2-3-2 Control Registers The memory control register is a four-bit register that sets up wait-count at a time of access to a base address of interrupt vector table and a special register zone.

  • Page 45: Interrupts

    2-4 Interrupts 2-4-1 Accepting and Returning from Interrupts In the MN101C00 series, when an interrupt is accepted, the hardware pushes the program's return address and the PSW, on to the stack, and branches to the beginning address of the interrupt program specified by the interrupt vector table.
  • Page 46 Chapter 2 Basic CPU Functions Interrupts Operation when Returning from Interrupt After the program POPs the register and other values saved by the interrupt service routine, an RTI instruction is implemented to return to the program that was being executed when the interrupt was received. The processing sequence for the return from interrupt instruction, RTI, is listed below.

  • Page 47: Interrupt Sources And Vector Addresses

    2-4-2 Interrupt Sources and Vector Addresses In addition to reset, there are 20 interrupt vectors that indicate the starting addresses of interrupt programs. These vectors are located in the 80-byte ROM address area X'04004' to X'04053'. Table 2-4-1 Interrupt Control Registers Interrupt Source Vector Number Reset...

  • Page 48: Interrupt Control Registers

    Chapter 2 Basic CPU Functions Be sure to use the MIE flag of the PSW register to write to all interrupt control registers. NMICR By setting xxxLVn to '11' (level IRQnICR 3), the corresponding interrupt vector will disabled, regardless of the state of the interrupt enable and interrupt request flags.
  • Page 49 Internal Interrupt Control Registers (TMnICR, TBICR, SCOICR, ATCICR, ADICR) The internal interrupt control registers (TMnICR, TBICR, SCnICR, ATCICR, ADICR) control the interrupt levels of internal interrupts, timer interrupts, serial interrupts, A/D conversion complete interrupts, and interrupt request/enable. Be sure to disable all interrupts before writing to these registors. TMnICR, TBICR, SCnICR, xxxLV1 xxxLV0 –...

  • Page 50: Reset

    Chapter 2 Basic CPU Functions For the reset to be stable, the low pulse must be maintained for at least four clock cycles. However, it is important to minimize noise, since a reset may occur in a smaller number of clock cycles. Reset 2-5 Reset The CPU contents are reset and registers are initialized when the RST pin is...

  • Page 51: Chapter 3 Port Functions

    Chapter 3 Port Functions...

  • Page 52: Overview

    Chapter 3 Port Functions Overview 3-1 Overview A total of 39 pins on the MN101C117, including those shared with special function pins, are allocated for the 7 ports of P0 to P2, P6 to P8, and PA. Each I/O port is assigned according to the special function register area in memory.
  • Page 53 Port 1 (P1) 5-bit CMOS tri-state I/O port. Table 3-1-3 Port 1 Functions Pin Name Type Dual Function P10 to P14 I/O RMOUT, TM2IO to TM4IO Port 2 (P2) 4-bit CMOS tri-state input port. Table 3-1-4 Port 2 Functions Pin Name Type Dual Function P20 to P23...
  • Page 54 Chapter 3 Port Functions Overview Port 7 (P7) 8-bit CMOS tri-state I/O port. Table 3-1-6 Port 7 Functions Pin Name Type Dual Function P70 to P71 I/O Port 8 (P8) 8-bit CMOS tri-state I/O port. Table 3-1-7 Port 8 Functions Pin Name Type Dual Function...

  • Page 55: Port Control Registers

    3-2 Port Control Registers 3-2-1 Overview 28 registers control the I/O ports. See table 3-2-1. Table 3-2-1 I/O Port Control Registers (1/2) Name Address X'03F10' P0OUT X'03F11' P1OUT X'03F12' P2OUT X'03F16' P6OUT X'03F17' P7OUT X'03F18' P8OUT X'03F20' P0IN X'03F21' P1IN P2IN X'03F22' X'03F26'...
  • Page 56 Chapter 3 Port Functions P6DIR P7DIR P8DIR P1OMD PAIMD P0PLU P1PLU P2PLU P6PLU P7PLUD P8PLU PAPLUD FLOAT1 Port Control Registers Table 3-2-1 I/O Port Control Registers (2/2) Name Address X'03F36' X'03F37' X'03F38' X'03F39' X'03F3A' X'03F40' X'03F41' X'03F42' X'03F46' X'03F47' X'03F48' X'03F4A' X'03F4B' Function...
  • Page 57 P0OUT P0OUT6 P1OUT P2OUT P2OUT7 P0IN6 P0IN P1IN P2IN P0DIR P0DIR6 P1DIR P1OMD P0PLU P0PLU6 P1PLU P2PLU P6OUT P6OUT5 P6OUT4 P6OUT3 P6OUT2 P6OUT1 P6OUT0 P6OUT7 P6OUT6 P6IN P6IN7 P6IN6 P6IN5 P6IN4 P6IN3 P6IN2 P6IN1 P6IN0 P6DIR7 P6DIR6 P6DIR5 P6DIR4 P6DIR3 P6DIR2 P6DIR1 P6DIR0 P6DIR P6PLU7 P6PLU6 P6PLU5 P6PLU4 P6PLU3 P6PLU2 P6PLU1 P6PLU0 P6PLU...
  • Page 58 Chapter 3 Port Functions P7OUT P8OUT P8OUT7 P7IN P8IN P8IN7 PAIN7 PAIN P7DIR P8DIR P8DIR7 PAIMD PAAIN7 P7PLUD P8PLU7 P8PLU PAPLUD7 PAPLUD Port Control Registers P8OUT6 P8OUT5 P8OUT4 P8OUT3 P8OUT2 P8OUT1 P8OUT0 P8IN6 P8IN5 P8IN4 P8IN3 P8IN2 P8IN1 P8IN0 PAIN6 PAIN5 PAIN4 PAIN3 PAIN2 PAIN1 PAIN0 P8DIR6 P8DIR5 P8DIR4 P8DIR3 P8DIR2 P8DIR1 P8DIR0...

  • Page 59: I/O Port Control Registers

    3-2-2 I/O Port Control Registers This section describes the special function registers that control the MN101C117's I/O ports. Data Registers • PnOUT registers Data registers to output to the ports. Data written to these registers is output from the ports. Low (Vss level) is output.
  • Page 60 Chapter 3 Port Functions Setting the PAIMD register prevents unnecessary current from flowing in a pin when an intermediate voltage (analog voltage) is applied to the pin. FLOAT1 Port Control Registers Port Output/Input Mode Registers • PnOMD/PnIMD registers These register settings determine whether the port pins(P10 to P14, PA0 to PA5) are used as I/O ports or as special function pins (dual function).

  • Page 61: I/O Port Configuration And Functions

    3-3 I/O Port Configuration and Functions P00,P02,P10 to P14 Pull-up resistor control I/O direction control Port output data Port input data Special function input data Special function output control Special function output data Pull-up Control bit resistor Register control (address) Control bit direction Register...
  • Page 62 Chapter 3 Port Functions Pull-up resistor control I/O direction control Port output data Port input data Special function input data I/O Port Configuration and Functions Reset Write Read Reset Write Read Reset Write Read Read Control bit Pull-up resistor Register control (address) Control bit...
  • Page 63 PA0 to PA7 Pull-up/pull-down resistor control Pull-up/pull-down resistor selection Port input data Input mode control Analog input Control bit Pull-up PAPLUD0 PAPLUD1 PAPLUD2 PAPLUD3 PAPLUD4 PAPLUD5 PAPLUD6 PAPLUD7 resistor Register control (address) Pull-up/ Control bit pull-down Register resistor (address) control Control bit PAAIN0 PAAIN1 PAAIN2 PAAIN3 Input mode...
  • Page 64 Chapter 3 Port Functions Pull-up resistor control Port input data Special function input data * P23 is only for 48-pin package. I/O Port Configuration and Functions Pin Configuration for P20, P22 to P23 Reset Write Read Read Control bit P2PLU0 P2PLU2 Pull-up resistor Register...
  • Page 65 Pull-up resistor control Read Special function input data Read Port input data Special function input data Control bit Pull-up resistor Register control (address) Control bit Port input Register (address) Special function Special function Control bit input Register selection (address) Figure 3-3-5 Configuration and Functions of P21 Reset Read Reset...
  • Page 66 Chapter 3 Port Functions Port output data I/O Port Configuration and Functions Schmitt trigger input Reset signal input Reset Write Special input Soft reset output Special function Special Control bit function output Register (address) Figure 3-3-6 Configuration and Functions of P27 P2OUT7 P2OUT (x'03F12')
  • Page 67 P70 to P71 Pull-up/pull-down resistor control Write Pull-up/pull-down resistor selection Write I/O direction control Write Port output data Write Port input data Pull-up/ Control bit pull-down Register resistor control (address) Control bit Pull-up/ pull-down Register resistor control (address) Control bit I/O direction Register control...
  • Page 68 Chapter 3 Port Functions Pull-up resistor control I/O direction control Port output data Port input data Port output Port output I/O Port Configuration and Functions P60 to P67,P80 to P87 Reset Write Read Reset Write Read Reset Write Read Read P6PLU0 P6PLU1 P6PLU2 P6PLU3 P6PLU4 Pull-up Control bit...

  • Page 69: Chapter 4 Timer Functions

    Chapter 4 Timer Functions...

  • Page 70: Overview

    Chapter 4 Timer Functions Overview 4-1 Overview The MN101C117 contains three 8-bit timers, one 16-bit timer, a watchdog timer, a time base timer, and circuits for remote control output and buzzer output. Table 4-1-1 Summary of Timer Functions Timer 2 (8-bit) Interrupt TM2IRQ...
  • Page 71 Chapter 4 Timer Functions Figure 4-1-1 Timers 2, 3 Block Diagram Overview...
  • Page 72 Chapter 4 Timer Functions Figure 4-1-2 Timer 4 Block Diagram Overview...
  • Page 73 Chapter 4 Timer Functions Figure 4-1-3 Timer 5/Time Base Block Diagram Overview...
  • Page 74 Chapter 4 Timer Functions Refer to the aragraph [1-6-1 ROM option] Overview Figure 4-1-4 Watchdog Timer, Buzzer Block Diagram...
  • Page 75 Chapter 4 Timer Functions Figure 4-1-5 Remote Control Transmission Block Diagram Overview...

  • Page 76: 8-Bit Timer Operation (Timers 2, 3)

    Chapter 4 Timer Functions 8-bit Timer Operation (timers 2, 3) 4-2 8-bit Timer Operation (timers 2, 3) 4-2-1 Overview Functions for timers 2 and 3 are listed below. Table 4-2-1 Summary of 8-bit Timer Functions Interrupt Timer operation Event counter Timer pulse output Serial transmission clock...

  • Page 77: Operation

    4-2-2 Operation Timer Operation (timers 2, 3) Settings for timer operation are listed below. Timer 2 is used as an example. Set the TM2EN flag of the timer 2 mode register (TM2MD) to "0" to stop the count operation of timer 2. Set the TM2CK2 0 flags of the TM2MD register to select fs, fs/4, fx, or synchronized fx as the clock source.
  • Page 78 Chapter 4 Timer Functions If TM2IO input is selected as the clock source and the value of binary counter 2 is to be read during operation, select synchronized TM2IO input to avoid reading data that may be incomplete during count-up transitions.
  • Page 79 Timer Pulse Output Function (timers 2, 3) Settings for the timer pulse output function are listed below. Timer 2 is used as an example. Set the TM2EN flag of the timer 2 mode register (TM2MD) to "0" to stop the count operation of timer 2.
  • Page 80 Chapter 4 Timer Functions If the TM3PWM flag of the TM3MD register is set to "1" and timer 2 PWM output is selected, the PWM output of timer 2 will also be output from the TM3IO pin. If port 1 is to be used as a PWM output pin, the P1DIR and P1PLU registers must be set.
  • Page 81 Chapter 4 Timer Functions Clock PWM output Figure 4-2-5 PWM Output Timing (when TM2OC register is X'00') Matches TM2OC register Overflow Binary counter 2 PWM output Figure 4-2-6 PWM Output Timing (when TM2OC register is X'FF') 8-bit Timer Operation (timers 2, 3)
  • Page 82 Chapter 4 Timer Functions The clock source for the serial interface has a frequency that is 1/2 of the overflow output of timer For serial interface settings, refer to the chapter on serial functions. Disable the timer 2 interrupt. 8-bit Timer Operation (timers 2, 3) Serial Transfer Clock Function(timer 3) Settings for the serial transfer clock function are listed below.

  • Page 83: 16-Bit Timer Operation (Timer 4)

    4-3 16-bit Timer Operation (timer 4) 4-3-1 Overview Timer 4 is a 16-bit programmable counter that can be used as an event counter. A signal with a frequency of 1/2 of the timer 4 overflow signal can be output from the TM4IO pin.
  • Page 84 Chapter 4 Timer Functions Clock TM4EN Binary counter 4 16-bit Timer Operation (timer 4) Figure 4-3-1 Binary Counter 4 (TM4BC) Count Timing If the TM4EN flag of the TM4MD register is changed simultaneously with other bits, the switching operation may cause binary counter 4 to be incremented.
  • Page 85 Event Count Function Settings for the event count function are listed below. Set the TM4EN flag of the timer 4 mode register (TM4MD) to "0" to stop the count operation of timer 4. Use the TM4CK2 to 0 flags of the TM4MD register to select TM4IO input or synchronized TM4IO input as the clock source.
  • Page 86 Chapter 4 Timer Functions The period of the output signal from the port is 1/2 of the period set in the TM4OCH, TM4OCL register. Binary counter 4 TM4OUT 16-bit Timer Operation (timer 4) Timer Pulse Output Function Settings for the timer pulse output function are listed below. Set the TM4EN flag of the timer 4 mode register (TM4MD) to "0"...
  • Page 87 Pulse Added Type PWM Output Function In the pulse added method, a 1-bit output is appended to the basic component of the 8-bit PWM output. Precise control is possible based on the number of PWM repetitions (256 times) to which this bit is appended. Settings for the pulse added type PWM output function are listed below.
  • Page 88 Chapter 4 Timer Functions 5-2-3 "Serial Interface Transfer Timing"] TM4OCH Register setting value X '00' X '01' X '02' X '04' X '08' X '10' Position of added pulse X'87' 16-bit Timer Operation (timer 4) Setting the Added Pulse Position The upper 8 bits of compare register 4 (TM4OCH) set the position of the added pulse.
  • Page 89 Capture Function Settings for the capture function are listed below. Set the TM4EN flag of the timer 4 mode register (TM4MD) to "0" to stop the count operation of timer 4. Use the TM4CK2 to 0 flags of the TM4MD register to select fosc, fs/4, or fs/16 as the clock source.

  • Page 90: 8-Bit Timer Operation (Timer 5)

    Chapter 4 Timer Functions When servicing an interrupt, reset the timer 5 interrupt request flag before starting timer 5. When choosing either time base timer output or time base timer synchronized output for the timer 5 clock source, the time base must be set up.

  • Page 91: Time Base Operation

    4-5 Time Base Operation 4-5-1 Overview The clock source for the time base timer can be set to fosc or fx. Also, the interrupt period for time base timer (TBIRQ) can be set to 1/2 clock source. 4-5-2 Operation Time Base Function Settings for the time base function are listed below.

  • Page 92: Watchdog Timer Operation

    Chapter 4 Timer Functions The upper 2 bits of the watchdog timer are cleared when the WDEN flag is set to "0." Therefore, if WDEN flag is set to 0 when an uppermost bit of a watchdog timer is 1, WDT interrupt occurs depending on the timing of this clear the watchdog timer may be reset at 1/4T...

  • Page 93: Remote Control Output Operation

    4-7 Remote Control Output Operation 4-7-1 Overview A remote control carrier pulse can be generated using the overflow of timer 3. Two duty ratios of 1/2 or 1/3 can be selected. 4-7-2 Setup and Operation Set the RMOEN flag of the remote control carrier output control register (RMCTR)to "0"...

  • Page 94: Buzzer Output

    Chapter 4 Timer Functions Buzzer Output 4-8 Buzzer Output 4-8-1 Buzzer Output Setup and Operation The square wave having a frequency 1/2 output from the P06/BUZZER pin. Set the BUZOE flag of the oscillation stabilization wait control register (DLYCTR) to "0" so that the buzzer output is turned off. Set the buzzer output frequency with the BUZCK1 and BUZCK0 flags of the DLYCTR.

  • Page 95: Timer Function Control Registers

    4-9 Timer Function Control Registers 4-9-1 Overview 19 registers control the timers. See table 4-9-1. Table 4-9-1 Timer Control Registers Name Address TM2OC X’03F72’ TM2BC X’03F62’ TM2MD X’03F82’ TM3OC X’03F73’ TM3BC X’03F63’ TM3MD X’03F83’ TM4OCL X’03F74’ TM4OCH X’03F75’ TM4BCL X’03F64’ TM4BCH X’03F65’...

  • Page 96: Programmable Timer/Counters

    Chapter 4 Timer Functions Timer Function Control Registers 4-9-2 Programmable Timer/Counters Timers 2~5 all contain a programmable 8-bit timer/counter (16-bit in timer 4). Programmable timer/counters consist of a compare register and a binary counter. (1) Compare register 2 (TM2OC) TM2OC7 TM2OC6 TM2OC5 TM2OC4...
  • Page 97 (5) Compare register 4 (TM4OCL) (lower 8 bits) TM4OCL7 TM4OCL6 TM4OCL5 TM4OCL4 TM4OCL3 Figure 4-9-5 Compare Register 4 (TM4OCL: X'03F74', R/W) (6) Compare register 4 (TM4OCH) (upper 8 bits) TM4OCH7 TM4OCH6 TM4OCH5 TM4OCH4 TM4OCH3 Figure 4-9-6 Compare Register 4 (TM4OCH: X'03F75', R/W) (7) Binary counter 4 (TM4BCL) (lower 8 bits) TM4BCL7 TM4BCL6...
  • Page 98 Chapter 4 Timer Functions Timer Function Control Registers (9) Input capture register (TM4ICL) (lower 8 bits) TM4ICL7 TM4ICL6 TM4ICL5 TM4ICL4 TM4ICL3 Figure 4-9-9 Input Capture Register (TM4ICL: X'03F66', R) (10) Input capture register (TM4ICH) (upper 8 bits) TM4ICH7 TM4ICH6 TM4ICH5 TM4ICH4 TM4ICH3 Figure 4-9-10 Input Capture Register (TM4ICH: X'03F67', R)

  • Page 99: Timer Mode Registers

    4-9-3 Timer Mode Registers Four readable and writable 6-byte timer mode registers. Control timers 2, 3, 4, 5, and the time base. (1) Timer 2 mode register (TM2MD) – – – TM2MD Figure 4-9-13 Timer 2 Mode Register (TM2MD: X'03F82', R/W) TM2EN TM2PWM TM2CK2...
  • Page 100 Chapter 4 Timer Functions – – – TM3MD Timer Function Control Registers (2) Timer 3 mode register (TM3MD) TM3EN TM3PWM TM3CK2 TM3CK1 TM3CK0 Figure 4-9-14 Timer 3 Mode Register (TM3MD: X'03F83', R/W) (at reset: ---00XXX) Clock source selection TM3CK2 TM3CK1 TM3CK0 fosc fs/4...
  • Page 101 (3) Timer 4 mode register (TM4MD) – TM4EN TM4PWM T4ICTS1 TM4MD Figure 4-9-15 Timer 4 Mode Register (TM4MD: X'03F84', R/W) T4ICTS0 TM4CK2 TM4CK1 TM4CK0 Chapter 4 Timer Functions (at reset: -0000XXX) Clock source selection TM4CK2 TM4CK1 TM4CK0 fosc fs/4 fs/16 TM4IO input Synchronous TM4IO input TM4 input capture trigger selection...
  • Page 102 Chapter 4 Timer Functions TM5MD TM5CLRS TM5IR2 TM5IR1 Timer Function Control Registers (4) Timer 5 mode register (TM5MD) TM5IR0 TM5CK3 TM5CK2 TM5CK1 TM5CK0 Figure 4-9-16 Timer 5 Mode Register (TM5MD: X'03F88', R/W) (at reset: 0XXXXXX0) Time base timer TM5CK0 clock source selection fosc (Use Prohibited) fx * * 48QFH package only...

  • Page 103: Timer Control Registers

    4-9-4 Timer Control Registers (1) Watchdog timer control register (WDCTR) – – – WDCTR Figure 4-9-17 Watchdog Timer Control Register (WDCTR: X'03F02', R/W) (2) Oscillation stabilization wait control register (DLYCTR) BUZCK1 BUZCK0 DLYCTR BUZOE Figure 4-9-18 Oscillation Stabilization Wait Counter Control Register (DLYCTR: X'03F03', R/W) –...
  • Page 104 Chapter 4 Timer Functions – RMCTR Timer Function Control Registers (3) Remote control carrier output control register (RMCTR) – – – – RMOEN RMDTY0 Figure 4-9-19 Remote Control Carrier Control Register (RMCTR: X'03F89', R/W) (at reset: ---00XX0) – Must be set to "0." Remote control carrier RMDTY0 output duty selection...

  • Page 105: Chapter 5 Serial Functions

    Chapter 5 Serial Functions...

  • Page 106: Overview

    Chapter 5 Serial Functions Overview 5-1 Overview The MN101C117 contains a serial interface that can operate in synchronous and simple UART modes. An overview of serial functions is shown below. Table 5-1-1 Overview of Serial Functions Interrupt Synchronous Simple UART Clock selection 1/8 period of clock Serial 0...
  • Page 107 Chapter 5 Serial Functions Figure 5-1-1 Serial 0 Block Diagram Overview...

  • Page 108: Synchronous Serial Interface

    Chapter 5 Serial Functions Section 5-2-3, "Serial Interface Transfer Timing"] Synchronous Serial Interface 5-2 Synchronous Serial Interface 5-2-1 Overview A serial interface begins operation when data is written to the shift buffer. A bit counter is incremented at each 1-bit transfer. The transfer is complete when the counter overflows.
  • Page 109 When the clock source is an external clock (SBT0 pin input): • Set the SC0SBTM flag of the SC0MD3 register. • Set bit 2 of the P0DIR register to input mode. • Set the P0PLU register, if necessary. Select the SC0SBOM flag of the SC0MD3 register. Select the SC0IOM flag of the SC0MD3 register.
  • Page 110 Chapter 5 Serial Functions Synchronous Serial Interface Clock Start condition enabled Start condition disabled Interrupt SC0BSY SC0LNG2 to 0 Figure 5-2-1 Synchronous Serial Interface Transmission Timing (falling edge) Clock Start condition enabled Start condition disabled Interrupt SC0BSY SC0LNG2 to 0 Figure 5-2-2 Synchronous Serial Interface Transmission Timing (rising edge)
  • Page 111 Reception Select the synchronous serial interface by setting the SC0CMD flag of the serial interface 0 control register (SC0CTR) to "0." Select the transfer bit count with the SC0LNG2 to 0 flags of the serial interface 0 mode register 0 (SC0MD0). The transfer bit count can be set as 1 to 8 bits.
  • Page 112 Chapter 5 Serial Functions Synchronous Serial Interface Clock Start condition enabled Start condition disabled Interrupt SC0BSY start condition enabled SC0BSY start condition disabled SC0LNG2 to 0 Figure 5-2-3 Synchronous Serial Interface Reception Timing (reception at rising edge) Clock Start condition enabled Start condition disabled...

  • Page 113: Serial Interface Transfer Timing

    5-2-3 Serial Interface Transfer Timing Serial interface 0 uses the SC0CE0 and SC0CE1 flags of serial interface 0 mode register 0 (SC0MD0), to control the edge at which transmission data is output and the edge at which reception data is input. During transmission, when the SCnCE1 flag is "0,"...
  • Page 114 Chapter 5 Serial Functions Synchronous Serial Interface When serial interface 0 is used for simultaneous transmission and reception, set the SCnCE0 and SCnCE1 flags of the SCnMD0 register to "00" or "01", so that the reception data input edge is opposite in polarity to the transmit data output edge. Also, the polarity of the reception data input edge is opposite polarity of the transmit data output edge of the other device.

  • Page 115: Half-Duplex Uart Serial Interface

    5-3 Half-duplex UART Serial Interface 5-3-1 Overview Setup and operation of UART transmission and reception are described below. 5-3-2 Setup and Operation Transmission Select UART by setting the SC0CMD flag of the serial interface 0 control register (SC0CTR) to "1." Specify the first bit to be transferred (MSB first or LSB first) with the SC0DIR flag of the serial interface 0 mode register 0 (SC0MD0).
  • Page 116 Chapter 5 Serial Functions Serial interface 0 begins operation when the SC0SBOS flag or the SC0SBIS flag is set to "1." Set the SC0SBOS flag or the SC0SBIS flag after all conditions have been set. Parity enabled Parity disabled Interrupt Parity enabled Interrupt Parity disabled...
  • Page 117 Reception Select UART by setting the SC0CMD flag of the serial interface 0 control register (SC0CTR) to "1." Specify the first bit to be transferred (MSB first or LSB first) with the SC0DIR flag of the serial interface 0 mode register 0 (SC0MD0). Select the valid edge of the clock signal with the SC0CE1 to 0 flags of the SC0MD0 register.
  • Page 118 Chapter 5 Serial Functions Parity enabled Parity disabled Interrupt Parity enabled Interrupt Parity disabled SC0BSY Parity enabled SC0BSY Parity disabled Half-duplex UART Serial Interface Figure 5-3-2 UART Reception Timing Parity Stop Stop Stop Stop...

  • Page 119: How To Use The Baud Rate Timer

    5-3-3 How to Use the Baud Rate Timer Refer to the following when using the baud rate timer to set the UART transfer speed. (1) Specifying the timer clock source The clock source is specified by the TM3CKS3 to 1 flags of the timer 3 mode register (TM3MD).

  • Page 120: Serial Interface Control Registers

    Chapter 5 Serial Functions Serial Interface Control Registers 5-4 Serial Interface Control Registers 5-4-1 Overview 7 registers control the serial interface. See table 5-4-1. Table 5-4-1 Serial Interface Registers Name Address SC0MD0 X'03F50' SC0MD1 X'03F51' SC0MD2 X'03F52' SC0MD3 X'03F53' SC0CTR X'03F54' SC0TRB X'03F55'...

  • Page 121: Transmit/Receive Shift Registers, Receive Data Buffer

    5-4-2 Transmit/Receive Shift Registers, Receive Data Buffer (1) Serial interface 0 transmit/receive shift register (SC0TRB) This 8-bit, writable register shifts the transmission data and the reception data. The direction of transfer can be specified as LSB first or MSB first. SC0TRB SC0TRB7 SC0TRB6...

  • Page 122: Serial Interface Mode Registers

    Chapter 5 Serial Functions SC0MD0 – SC0CE0 SC0CE1 SC0DIR Serial Interface Control Registers 5-4-3 Serial Interface Mode Registers (1) Serial interface 0 mode register (SC0MD0) SC0STE SC0LNG2 SC0LNG1 SC0LNG0 Figure 5-4-3 Serial Interface 0 Mode Register 0 (SC0MD0: X'03F50', R/W) (at reset: -00XX000) Transfer bit count SC0LNG2...
  • Page 123 (2) Serial interface 0 mode register 1 (SC0MD1) SC0MD1 – – SC0CKM SC0CK1 Figure 5-4-4 Serial Interface 0 Mode Register 1 (SC0MD1: X'03F51', R/W) SC0CK0 SC0BRKF SC0ERE SC0TRI Chapter 5 Serial Functions (at reset: --X00000) Transmit/receive SC0TRI interrupt request flag Transmit interrupt request Receive interrupt request SC0ERE...
  • Page 124 Chapter 5 Serial Functions SC0MD2 – – SC0BRKE Serial Interface Control Registers (3) Serial interface 0 mode register 2 (SC0MD2) SC0FM1 SC0FM0 SC0PM1 SC0PM0 SC0NPE Figure 5-4-5 Serial Interface 0 Mode Register 2 (SC0MD2: X'03F52', R/W) (at reset: --000XXX) SC0NPE Parity enable Parity enabled Parity disabled...
  • Page 125 (4) Serial interface 0 mode register 3 (SC0MD3) SC0MD3 – – SC0IOM SC0SBOM Figure 5-4-6 Serial Interface 0 Mode Register 3 (SC0MD3: X'03F53', R/W) SC0SBTM SC0SBOS SC0SBIS SC0SBTS Chapter 5 Serial Functions (at reset: --000000) SC0SBTS SBT0 pin function selection Port Serial clock pin SC0SBIS...

  • Page 126: Serial Interface Control Register

    Chapter 5 Serial Functions SC0CTR SC0BSY SC0CMD – Serial Interface Control Registers 5-4-4 Serial Interface Control Register (1) Serial interface 0 control register (SC0CTR) – SC0FEF SC0PEK SC0ORE – Figure 5-4-7 Serial Interface 0 Control Register (SC0CTR: X'03F54', R) (R/W available with SC0CMD only) (at reset: 00XX000X) SC0ORE Overrun error detection...

  • Page 127: Chapter 6 A/D Conversion Functions

    A/D Conversion Chapter 6 Functions...

  • Page 128: Overview

    Chapter 6 A/D Conversion Functions ANCTR0 ANCHS0 ANCHS1 ANCHS2 ANLADE ANCK0 ANCK1 ANSH0 ANSH1 Overview 6-1 Overview The MN101C117 has an internal A/D converter with 10-bit resolution. A sample-and-hold circuit is contained on-chip and software can switch the analog input between channels 0 to 7 (AN0 to AN7). When the A/D converter is stopped, power consumption can be reduced by turning off the internal ladder resistors.

  • Page 129: A/D Conversion

    6-2 A/D Conversion The procedures for operating the A/D conversion circuit are listed below. (1) Set the ANCHS2 to ANCHS0 flags of A/D control register 0 (ANCTR0) to specify one of pins AN7 to AN0 (PA7 to PA0) as the analog input. (2) Set the ANCK1 and ANCK0 flags of A/D control register 0 to select the A/D conversion clock.
  • Page 130 Chapter 6 A/D Conversion Functions A/D Converter Control Registers The following items must be implemented to maintain the accuracy of the A/D converter: 1. Use a maximum input pin impedance, R, of 500kΩ capacitor, C, that is minimum 1,000pF and maximum 1µF 2.

  • Page 131: A/D Converter Control Registers

    6-3 A/D Converter Control Registers 6-3-1 Overview Four registers control the A/D converter. See table 6-3-1. Table 6-3-1 A/D Converter Control Registers Name Address ANCTR0 X'03F90' ANCTR1 X'03F91' ANBUF0 X'03F92' ANBUF1 X'03F93' Function A/D control register 0 A/D control register 1 A/D buffer 0 A/D buffer 1 Chapter 6 A/D Conversion Functions...

  • Page 132: A/D Control Register (Anctr)

    Chapter 6 A/D Conversion Functions ANSH1 ANSH0 ANCK1 ANCTR0 A/D Converter Control Registers 6-3-2 A/D Control Register (ANCTR) This readable and writable 8-bit register controls the operation of the A/D converter. ANCK0 ANLADE ANCHS2 ANCHS1 ANCHS0 (1) A/D control register 0 (ANCTR0) 1:Specify that where the period of the A/D conversion clock is greater than 800ns.
  • Page 133 (2) A/D conversion control register 1 (ANCTR1) ANCTR1 ANST Figure 6-3-2 A/D Control Register 1 (ANCTR1: X'03F91', R/W) Chapter 6 A/D Conversion Functions (at reset: 0-------) A/D conversion status ANST A/D conversion completed or stopped A/D conversion started or in progress A/D Converter Control Registers...

  • Page 134: A/D Buffers (Anbuf)

    Chapter 6 A/D Conversion Functions 6-3-3 A/D Buffers (ANBUF) These read-only registers store the A/D conversion results. (1) A/D buffer 0 (ANBUF0) This register stores the lower 2 bits of the A/D conversion results. ANBUF0 ANBUF07 ANBUF06 Figure 6-3-3 A/D Buffer 0 (ANBUF0: X'03F92', R) (2) A/D buffer 1 (ANBUF1) This register stores the upper 8 bits of the A/D conversion results.

  • Page 135: Chapter 7 Ac Zero-Cross Circuit/Noise Filter

    AC Zero-Cross Chapter 7 Circuit/Noise Filter...

  • Page 136: Overview

    Chapter 7 AC Zero-Cross Circuit/Noise Filter P21/IRQ1/SENS Overview 7-1 Overview The P21/SENS pin is the input pin for the AC zero-cross detection circuit. The AC zero-cross detection circuit outputs a high level when the input is at an intermediate level, and a low level at all other times. FLOAT1 P7RDWN PARDWN...

  • Page 137: Ac Zero-Cross Circuit Operation

    7-2 AC Zero-Cross Circuit Operation 7-2-1 Setup and Operation Settings for zero-cross circuit operation are listed below. (1) Set the REDG1 flag of the IRQ1ICR register to select the valid edge for IRQ1. (2) Set the NF1EN and NF1CK1 to 0 flags of the NFCTR register to set the noise filter and its sampling clock.

  • Page 138: Noise Filter

    Chapter 7 AC Zero-Cross Circuit/Noise Filter IRQ0: External interrupt 0 IRQ1: External interrupt 1 P21/IRQ1/SENS Noise Filter 7-3 Noise Filter 7-3-1 Overview External interrupt pins IRQ0 and IRQ1 contain noise filtering circuit. This circuitry can be used for remote control signal reception. fs/2 fs/2 fs/2...

  • Page 139: Example Input And Output Waveforms For Noise Filter

    7-3-2 Example Input and Output Waveforms for Noise Filter When the noise filter is used, the waveform input to the IRQ0 pin is sampled based on the clock specified by the NF0CKS0 and NF0CKS1 flags of the noise filter control register (NFCTR).

  • Page 140: Ac Zero-Cross Control Register

    Chapter 7 AC Zero-Cross Circuit/Noise Filter 2-4-3 "Interrupt Control Registers External Interrupt Control Registers"] 3-2-2 "I/O Port Control Registers Pin Control Registers"] AC Zero-Cross Control Register 7-4 AC Zero-Cross Control Register 7-4-1 Overview Four registers control the AC zero-cross circuit. Table 7-4-1 AC Zero-Cross Control Register Name Address...

  • Page 141: Noise Filter Control Register (Nfctr)

    7-4-2 Noise Filter Control Register (NFCTR) This 6-bit readable and writable register controls the noise filter. – – NF1CKS1 NF1CKS0 NFCTR Figure 7-4-1 Noise Filter Control Register (NFCTR: X'03F8A', R/W) NF1EN NF0CKS1 NF0CKS0 NF0EN Chapter 7 AC Zero-Cross Circuit/Noise Filter (at reset: --000000) NF0EN IRQ0 noise filter setup and operation...
  • Page 142 Chapter 7 AC Zero-Cross Circuit/Noise Filter...

  • Page 143: Appendices

    Appendices...

  • Page 144: Eprom Versions

    256Kbit EPROM(Vpp=12.5V, tpw=0.2ms). Therefore, by replacing theEPROM Version's 42-pin socket with a special 28-pin socket adapter(supplied by Panasonic) having the same configuration as a normal EPROM, a general-purpose EPROM writer can be used to perform read and write operations.

  • Page 145: Cautions On Use

    8-1-2 Cautions on Use EPROM Versions differs from the MN101C11* in some of its electrical characteristics. The user should be aware of these differences. (1) To prevent data from being erased by ultraviolet light after a program is written, affix seals impermeable to UV rays to the glass sections at the top and side sections of the CPU.

  • Page 146: Erasing Written Data In Windowed Packages

    Chapter 8 Appendices EPROM Versions 8-1-3 Erasing Written Data in Windowed Packages (PX-AP101C11-SDC, PX-AP101C11-FBC) In an internal EPROM with windowed packaging, data is erased("0" when UV light at 253.7nm permeates the window to irradiate the chip. The recommended exposure is 10W · s/cm by using a commercial UV lamp positioned 2 to 3cm above the package for 15-20 minutes(when the illumination intensity of the package surface is12000...

  • Page 147: Characteristics Of Eprom Versions

    8-1-4 Characteristics of EPROM Version The MN101C11*(mask ROM version) and the Microcomputer with internal EPROM version have the following differences. Table 8-1-1 Difference between MN101C*(Mask ROM version) and Internal EPROM version) Operating temperature 4.5 to 5.5V（0.1μs/20MHz） 2.7 to 5.5v（0.25μs/8MHz）     Operating voltage 2.0 to 5.5v（1.00μs/2MHz）...

  • Page 148: Writing To Internal Eprom

    Chapter 8 Appendices Package type 42-SDIP 44-QFP 48-QFH No.1 Pin No.1 Pin (PX-AP101C11-SDC) (top view) EPROM Versions 8-1-5 Writing to Microcomputer with Internal EPROM Fit in the writing adapter and position the No.1 pin. No.1 pin must be matched to this position.
  • Page 149 ROM writer Selection The device names should be set up as listed below. Table 8-1-2 Device selection Equip. name Vendor Pecker 30 Avarl Data 1890A Minato Electronics Lab Site Data I/O The above settings are based on the standard samples. When you use the other equipment than the ones listed, contact the nearest semiconductor design center.(Refer to the sales office table attached at the end of the manual.)

  • Page 150: Cautions On Handling The Rom Writer

    Chapter 8 Appendices EPROM Versions 8-1-6 Cautions on Operating the ROM Writer Cautions on operating the ROM writer (1)The Vpp programming voltage for the EPROM versions is 12.5V. Programming with a 21-volt ROM writer can lead to damage. The ROM writer specifications must match those for standard 1-megabit EPROMS:Vpp=12.5V V;tpw=0.2ms.

  • Page 151: Option Bit

    8-1-7 Option Bit The MN101C117 and the MN101CP117 control the oscillation mode after resetting as well as the runaway-detection watch dog timer, using bit 2 to 0 of the last address (X'7FFF) of the built-in ROM. Option bit PKGSEL2 PKGSEL1 Fig.

  • Page 152: Writing Adapter Connection

    Chapter 8 Appendices EPROM Versions 8-1-8 Writing Adapter Connection NRST Package Code SDIP042-P-0600 Fig. 8-1-3 MN1-1CP117-DP(DC)EPROM Writing Adapter Connections Refer to the pin connection drawing of the 256-bit EPROM(27C256). OSC1 OSC2 MMOD...
  • Page 153 MN101CP117 Package code: QFP044-P-1010 Pin pitch: Fig. 8-1-4 MN101CP117-BL(BC)EPROM Writing Adapter Connections Refer to the pin connection drawing of the 256-bit EPROM(27C256). ４４- ＱＦＰ 0.8mm Chapter 8 Appendices EPROM Versions...
  • Page 154 Chapter 8 Appendices EPROM Versions MN101CP117 ４８- ＱＦＨ Package code: QFH048-P-0707 Pin pitch: Fig. 8-1-5 MN101CP117-HP EPROM Writing Adapter connections Refer to the pin connection drawing of the 256-bit EPROM(27C256). 0.5mm...

  • Page 155: Instruction Set

    8-2 Instruction Set MN101C00 SERIES INSTRUCTION SET Group Mnemonic Operation Data move instructions MOV Dn,Dm Dn Dm MOV imm8,Dm imm8 Dm MOV Dn,PSW Dn PSW MOV PSW,Dm PSW Dm MOV (An),Dm mem8(An) Dm MOV (d8,An),Dm mem8(d8+An) Dm MOV (d16,An),Dm mem8(d16+An) Dm...
  • Page 156 Chapter 10 Appendices MN101C00 SERIES INSTRUCTION SET Group Mnemonic Operation MOVW imm16,Am imm16 Am MOVW SP,Am SP Am MOVW An,SP An SP MOVW DWn,DWm DWn DWm MOVW DWn,Am DWn Am MOVW An,DWm An DWm MOVW An,Am An Am PUSH PUSH Dn...
  • Page 157 MN101C00 SERIES INSTRUCTION SET Group Mnemonic Operation NOT Dn Dn Dn ASR Dn Dn.msb temp,Dn.lsb CF Dn>>1 Dn,temp Dn.msb LSR Dn Dn.lsb CF,Dn>>1 Dn 0 Dn.msb ROR Dn Dn.Isb temp,Dn>>1 Dn CF Dn.msb,temp CF Bit manipulation instructions mem8(IOTOP+io8)&bpdata...PSW 0 ● 0 ● 5 BSET...
  • Page 158 Chapter 10 Appendices MN101C00 SERIES INSTRUCTION SET Group Mnemonic Operation BGT label if((VF^NF)|ZF=0),PC+6+d11(label)+H PC – if((VF^NF)|ZF=1),PC+6 PC BHI label if(CFIZF=0),PC+5+d7(label)+H PC – if(CFIZF=1), PC+5 PC BHI label if(CFIZF=0),PC+6+d11(label)+H PC – if(CFIZF=1), PC+6 PC BLS label if(CFIZF=1),PC+5+d7(label)+H PC – if(CFIZF=0), PC+5 PC BLS label if(CFIZF=1),PC+6+d11(label)+H PC –...
  • Page 159 MN101C00 SERIES INSTRUCTION SET Group Mnemonic Operation TBZ (io8)bp,label if(mem8(IOTOP+io8)bp=0),PC+7+d7(label)+H PC 0 if(mem8(IOTOP+io8)bp=1),PC+7 PC TBZ (io8)bp,label if(mem8(IOTOP+io8)bp=0),PC+8+d11(label)+H PC 0 if(mem8(IOTOP+io8)bp=1),PC+8 PC TBZ (abs16)bp,label if(mem8(abs16)bp=0),PC+9+d7(label)+H PC 0 if(mem8(abs16)bp=1),PC+9 PC TBZ (abs16)bp,label if(mem8(abs16)bp=0),PC+10+d11(label)+H PC 0 if(mem8(abs16)bp=1),PC+10 PC TBNZ TBNZ (abs8)bp,label if(mem8(abs8)bp=1),PC+7+d7(label)+H PC 0...
  • Page 160 Chapter 10 Appendices MN101C00 SERIES INSTRUCTION SET Group Mnemonic Operation mem8(SP)→(PC).bp7∼0 mem8(SP+1)→(PC).bp15∼8 mem8(SP+2).bp7→(PC).H mem8(SP+2).bp1∼0→(PC).bp17∼16 SP+3→SP mem8(SP)→PSW mem8(SP+1)→(PC).bp7∼0 mem8(SP+2)→(PC).bp15∼8 mem8(SP+3).bp7→(PC).H mem8(SP+3).bp1∼0→(PC).bp17∼16 mem8(SP+4)→HA-l mem8(SP+5)→HA-h SP+6→SP Control instruction REP imm3 imm3→RPC Note: "Page" refers to the corresponding page in the Instruction Manual. Instruction Set...

  • Page 161: Instruction Map

    8-3 Instruction Map MN101C00 SERIES INSTRUCTION MAP 1st nibble\2nd nibble MOV #8,(io8) RTI JSR d12(label) JSR d16(label) MOV #8,(abs8)/(abs12) PUSH An When the extension code is b'0010' When the extension code is b'0011' MOV (abs12),Dm MOV Dn,(abs12) MOV (io8),Dm MOV Dn,(io8)
  • Page 162 Chapter 10 Appendices Extension code: b'0011' 2nd nibble\3rd nibble TBZ (abs8)bp,d7 TBNZ (abs8)bp,d7 CMP Dn,Dm ADD Dn,Dm TBZ (io8)bp,d7 TBNZ (io8)bp,d7 OR Dn,Dm AND Dn,Dm BSET (io8)bp JMP abs18(label) A XOR Dn,Dm / XOR #8,Dm B ADDC Dn,Dm C BSET (abs16)bp D BTST (abs16)bp E TBZ (abs16)bp,d7 TBNZ (abs16)bp,d7...

  • Page 163: Special Function Registers

    Port 8 output P0IN6 P1IN4 P1IN3 Chapter 10 Appendices Reference Bit 2 Bit 1 Bit 0 page HALT OSC1 OSC0 MN101C00 seriesﾞ HALT LSI Manual Oscillation control transfer request IRWE WDEN Watchdog timer table DLYS1 DLYS0 Sets oscillation stabilization wait period...
  • Page 164 Chapter 10 Appendices Register Address Bit 7 X’ 3F24’ Disables to use Disables to use X’ 3F25’ P6IN7 X’ 3F26’ P6IN P7IN X’ 3F27’ P8IN7 P8IN X’ 3F28’ PAIN7 PAIN X’ 3F2A’ P0DIR X’ 3F30’ X’ 3F31’ P1DIR X’ 3F33’ Disables to use Disables to use X’...
  • Page 165 Register Address Bit 7 P2PLU X’ 3F42’ Disables to use X’ 3F43’ Disables to use X’ 3F44’ Disables to use X’ 3F45’ P6PLU7 P6PLU X’ 3F46’ X’ 3F47’ P7PLUD P8PLU7 P8PLU X’ 3F48’ PAPLUD7 PAPLUD X’ 3F4A’ FLOAT1 X’ 3F4B’ Disables to use X’...
  • Page 166 Chapter 10 Appendices Address Register X’ 3F59’ Disables to use X’ 3F5A’ Disables to use X’ 3F5B’ Disables to use X’ 3F5C’ Disables to use X’ 3F5D’ Disables to use X’ 3F60’ Disables to use Disables to use X’ 3F61’ X’...
  • Page 167 Register Address Bit 7 X’ 3FE0’ Disables to use NMICR X’ 3FE1’ IRQ0LV1 IRQ0LV0 X’ 3FE2’ IRQ0ICR Interrup level flag for external interrupt IRQ1LV1 IRQ1LV0 IRQ1ICR X’ 3FE3’ Interrupt level flag for external interrupt Disables to use X’ 3FE4’ Disables to use X’...
  • Page 168 Chapter 10 Appendices Register Address Bit 7 X’ 3FE0’ Disables to use NMICR X’ 3FE1’ IRQ0LV1 IRQ0LV0 X’ 3FE2’ IRQ0ICR Interrup level flag for external interrupt IRQ1LV1 IRQ1LV0 IRQ1ICR X’ 3FE3’ Interrupt level flag for external interrupt Disables to use X’...
  • Page 169 MN101C115 / 117 LSI User's Manual August,1999 1st Edition 1st Printing Issued by Matsushita Electric Industrial Co., Ltd. Matsushita Electronics Corporation © Matsushita Electric Industrial Co., Ltd. © Matsushita Electronics Corporation...
  • Page 170 Semiconductor Company Matsushita Electronics Corporation U.S.A. SALES OFFICE Panasonic Industrial Company New Jersey Office: 2 Panasonic Way, Secaucus, New Jersey 07094 Tel: 201-392-6173 Fax: 201-392-4652 Milpitas Office: 1600 McCandless Drive, Milpitas, California 95035 Tel: 408-945-5630 Fax: 408-946-9063 Chicago Office: 1707 N. Randall Road, Elgin, Illinois 60123-7847...

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