C Bus Interface Operation - Panasonic MN10285K User Manual

2
I C Bus Controller
Description
MN102H75K/F75K/85K/F85K LSI User Manual
Figure 13-3 shows the MN102H75K/85K operation sequence in each of these
2
modes. In all modes, the I
byte transfer, then the software loads the next data byte.
MN102H51K
R/W = 0
Address
Master S R/W
(7 bits)
Slave
Normally ACK = 0
MN102H51K
R/W = 1
Address
Master
S R/W
(7 bits)
Slave
Address
Master
S
(7 bits)
Slave
MN102H51K
When the microcontroller is addressed,
it outputs ACK = 0 and sets the AAS bit
of the I2CDREC register to 1.
Address
Master
S
(7 bits)
Slave
MN102H51K
When the microcontroller is addressed,
it outputs ACK = 0 and sets the AAS bit
of the I2CDREC register to 1.
Figure 13-3 I
295
Panasonic
C bus controller generates an interrupt after each data
Interrupt Interrupt
Data (8 bits)
ACK ACK
A. Master Transmitter
Interrupt Interrupt
ACK
ACK Data (8 bits)
B. Master Receiver
R/W = 1
Ack = 0
R/W ACK
ACK Data (8 bits)
Interrupt
C. Slave Transmitter
R/W = 0
R/W Data (8 bits)
ACK ACK
Interrupt
D. Slave Receiver
2

C Bus Interface Operation

Panasonic Semiconductor Development Company
Interrupt
Data (8 bits) P
ACK
ACK = 1 signals transfer
end to slave transmitter.
Interrupt
ACK P
Data (8 bits)
Ack = 1
ACK P
Data (8 bits)
Interrupt Interrupt
ACK = 1 signals transfer
end to slave transmitter.
Data (8 bits) P
ACK
Interrupt Interrupt
Interrupt
STS sets to 1.