Closed-Caption Decoder Registers; Closed-Caption Decoder Register; Panasonic - Panasonic MN10285K User Manual

Panax series microcomputer
Table of Contents

Advertisement

Panasonic Semiconductor Development Company
9.4

Closed-Caption Decoder Registers

All registers in Closed-caption Decoder block cannot be written by byte (by word
only). Read by byte is possible.
Table 9-9 Closed-Caption Decoder Register
CCD0
CCD1
Register
Address
Address R/W
FCCNT
x'007E00'
x'007E20'
MAXMIN
x'007E02'
x'007E22'
SLICE
x'007E04'
x'007E24'
HNUM
x'007E06'
x'007E26'
ACQ1
x'007E08'
x'007E28'
CAPDATA
x'007E0A'
x'007E2A'
CRIFA
x'007E0C'
x'007E2C'
CRIFB
x'007E0E'
x'007E2E'
CRI1S
x'007E10'
x'007E30'
CRI1E
x'007E12'
x'007E32'
CRI2S
x'007E14'
x'007E34'
CRI2E
x'007E16'
x'007E36'
DATAS
x'007E18'
x'007E38'
DATAE
x'007E1A'
x'007E3A'
STAP
x'007E1C'
x'007E3C'
FCPNUM
x'007E1E'
x'007E3E'
NFSEL
x'007EC0'
x'007EE0'
FQSEL
x'007EC2'
x'007EE2'
SCMING
x'007EC4'
x'007EE4'
BPPST
x'007EC6'
x'007EE6'
SYNCMIN
x'007EC8'
x'007EE8'
SPLV
x'007ECA'
x'007EEA'
CLAMP
x'007ECC'
x'007EEC'
HSEP1
x'007ECE'
x'007EEE'
HSEP2
x'007ED0'
x'007EF0'
FIELD
x'007ED2'
x'007EF2'
HLOCKLV
x'007ED4'
x'007EF4'
HDISTW
x'007ED6'
x'007EF6'
VCNT
x'007ED8'
x'007EF8'
HVCOND
x'007EDA'
x'007EFA'
CLPCND1
x'007EDC'
x'007EFC'
SBFNUM
x'007F4C'
x'007F6C'
TESTA
x'007F4E'
x'007F6E'
236

Panasonic

Closed-Caption Decoder
Closed-Caption Decoder Registers
Description
R/W
VBI decoding format select register
R
CRI interval maximum and minimum register
R/W
VBI data slice level register
R
HSYNC count register
R/W
ACQ capture timing control register 1
R
Caption data capture register
R
CRI frequency width register A
R
CRI frequency width register B
R/W
CRI capture start timing control register 1
R/W
CRI capture stop timing control register 1
R/W
CRI capture start timing control register 2
R/W
CRI capture stop timing control register 2
R/W
Data capture start timing control register
R/W
Data capture stop timing control register
R/W
Sampling start position register (software setting)
R
Sampling start position register (hardware calculation)
R/W
Noise filter select register
R/W
Frequency select register
R/W
Minimum sync level detection interval set register
R/W
Backporch position register
R
Sync and pedestal level register
R/W
Sync separator level set register
R/W
Clamping control register
R/W
HSYNC separator control register 1
R/W
HSYNC separator control register 2
R/W
Field detection control register
R/W
Sync separator detection control register 1
R/W
Sync separator detection control register 2
R/W
VSYNC separator control register
R
Sync separator status register
R
Clamping control signal status register 1
R
Sampling start position register
R
Test register
MN102H75K/F75K/85K/F85K LSI User Manual

Advertisement

Table of Contents
loading

This manual is also suitable for:

Mn102f75kMn102f85kMn102h75kMn102h85k

Table of Contents