Panasonic MN10285K User Manual page 150

Analog-to-Digital Converter
ADC Setup Examples
Do not change the clock source
once you have selected it.
Selecting the clock source while
you set up the count operation
control will corrupt the value in
the binary counter.
MN102H75K/F75K/85K/F85K LSI User Manual
To set up the input port:
Set the P0DIR[5:3] bits of the port 0 I/O control register (P0DIR) to 0. This sets
the ADIN2 (P05), ADIN1 (P04), and ADIN0 (P03) pins (P11) to general-purpose
input.
To set up the ADC:
Set the operating conditions in the ADC control register (ANCTR). Select
multiple-channel, single-conversion mode (ANMD[1:0] = b'01') and B
the clock source (ANCK[1:0] = b'10'). Set the conversion start/busy bit, ANEN,
to 0. Set ANTC to 1, enabling conversion start at timer 1 underflow. Set the
AN1CH[3:0] field to the first channel (channel 0) and set the ANNCH[3:0] to the
last channel (channel 2).
ANCTR (example)
Bit: 15 14 13 12
AN AN AN AN AN
NCH3 NCH2 NCH1 NCH0 1CH3
Setting: 0 0 1 0
To set up the conversion cycle
1. Set the divide-by ratio for timer 1. To divide B
(x'FF') to the timer 1 base register (TM1BR). (The valid range for TM1BR
is 1 to 255.)
TM1BR (example)
Bit: 7 6 5 4
TM1 TM1 TM1 TM1
BR7 BR6 BR5 BR4
Setting: 1 1 1 1
2. Set the TM1LD bit of the TM1MD register to 1 and the TM1EN bit to 0.
(This loads the value in the base register to the binary counter.)
TM1MD (example)
Bit: 7 6 5 4
TM1 TM1
— —
EN LD
Setting: 0 1 0 0
3. Set TM1LD to 0 and TM1EN to 1. This starts the timer. Counting begins at
the start of the next cycle.
When the binary counter (TM1BC) reaches 0, the microcontroller reloads the
value in the base register (TM1BR) to TM1BC and simultaneously generates a
timer 1 underflow interrupt. After each timer 1 underflow, the ADC converts
each of the ADIN[2:0] inputs a single time.
149
Panasonic
11 10 9 8 7 6
AN AN AN AN AN
1CH2 1CH1 1CH0 EN TC
0 0 0 0 0 1
3 2 1 0
TM1 TM1 TM1 TM1
BR3 BR2 BR1 BR0
1 1 1 1
3 2 1 0
TM1 TM1
— —
S1 S0
0 0 1 0
Panasonic Semiconductor Development Company
/8 as
OSC
x'00FDA0'
5 4 3 2 1
AN AN AN
— —
CK1 CK0 MD1 MD0
0 0 1 0 0
/4 by 256, write 255
OSC
x'00FE11'
x'00FE21'
0
AN
1