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SYSCLK or
divided SYSCLK output
P5IN0
Panasonic Semiconductor Development Company
0: Pullup off
1: Pullup on
P5PUP0
0: P50
1: SYSCLK
P5MD0
0: Port input
1: Port output
P5DIR0
0: Port low output
1: Port high output
P5OUT0
Figure 11-22 P50/SYSCLK (Port 5)
Panasonic
0
M
U
X
1
MN102H75K/F75K/85K/F85K LSI User Manual
272
I/O Ports
I/O Port Circuit Diagrams
Pin
P50/SYSCLK
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