H Counter Pins; H Counter Input Signal Timing; Panasonic - Panasonic MN10285K User Manual

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Figure 14-3 shows the input timing for the count source and reset signals. Never
input a count source signal in less than 245 ns (t
Otherwise, the signal may be counted as part of the previous count cycle.
Note: In this example, HI0 is active high and VSYNC is active low.
Figure 14-3 H Counter Input Signal Timing
The 10-bit counter counts the HSYNC signal from 0 to x'3FF', and the 10-bit
register stores the count. The H counter uses the four pins shown in table 14-1.
Table 14-1 H Counter Pins
Pin No.
Pin Name
H75K H85K
HI0 17
HI1 16
VI0 6
VSYNC 2
To use the H counter, set the port 4 and 5 output control registers (P4OUT and
P5OUT) to 0 and set the H counter pins to input.
To use HI0, set the P4DIR3 bit (x'00FFE4') to 0.
To use HI1, set the P4DIR4 bit (x'00FFE4') to 0.
To use VI0, set the P5DIR2 bit (x'00FFE5') to 0.
To use VSYNC, set the P5DIR4 bit (x'00FFE5') to 0.
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) after the reset signal input.
1
Description
45 Count source pin
46 Count source pin
53 Count reset pin
55 Count reset pin
MN102H75K/F75K/85K/F85K LSI User Manual
H Counter
H Counter Operation
Alternative Functions
P43/TM5IOB
P44/TM5IC
P52/IRQ4
P54/IRQ5