Setting Up I 2 C Reception Using Serial Interface 0; Master Receiver Timing In I - Panasonic MN10285K User Manual

Panax series microcomputer
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Serial Interfaces
Serial Interface Setup Examples
You do not need to enable
reception if it is already enabled
by the initial settings. You can
also omit any settings already in
place from the transmission
sequence.
The parity bits serve as the ACK
signal. To output an ACK = 1 sig-
nal, select a fixed parity of 1. To
output an ACK = 0 signal, select
a fixed parity of 0. Select a parity
of none if there is no ACK signal
MN102H75K/F75K/85K/F85K LSI User Manual
2
5.6.5
Setting Up I
C Reception Using Serial Interface 0
This example illustrates the microcontroller as a master receiver in the I
using the SBO0 and SBT0 pins.
When initiating master receiver mode, your program must always first transmit a
byte of data. The master reception occurs during the interrupt service routine that
runs after the data is transmitted. For an example setup of master transmission,
see section 5.6.4, "Setting Up I
page 137.
2
To set up the I
C interface:
1.
During the interrupt service routine for the serial transmission end, enable
reception by setting the SC0REN bit of SC0CTR to 1.
2.
Select ACK output of 1.
To set up data reception:
1.
Write a dummy data bit, x'FF', to the serial port 0 transmit/receive buffer.
This sets the SBO0 signal high and initiates the master receiver mode.
2.
During the service routine for the serial reception interrupt, the CPU reads
the transmit/receive buffer to retrieve the reception data. (A transmission
interrupt can serve as a reception interrupt.)
To set up the stop sequence:
1.
Set the SC0IIC bit of SC0CTR to 0 to signal the stop sequence.
2.
When you signal the stop sequence, the data reception is still in progress.
After the stop sequence is output, you must disable reception and reinitialize
reception for succeeding bytes.
Figure 5-14 shows an example timing chart.
2
I
C sequence
output bit
Write to
SC0TRB
SBO0 output
b7 b6 b5 b4 b3 b2 b1 b0
SBT0 output
Start detection bit = 1
Figure 5-14 Master Receiver Timing in I
139
Panasonic
2
C Transmission Using Serial Interface 0," on
Dummy data transmission for reception
ACK
b7
b6 b5 b4 b3 b2 b1 b0
Tx interrupt request
Rx settings
Data rx
2
C Mode (with ACK)
Panasonic Semiconductor Development Company
2
C mode,
ACK
Tx interrupt request
Stop detection bit = 1
Stop sequence

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