Table of Contents
Advertisement
Closed-Caption Decoder
Functional Description
Table 9-2 Caption decoder register setting
Use two cap-
caption 0
tion decoders
caption 1
Use one cap-
caption 0
tion decoder
no caption 1
No use caption
no caption 0
decoder
no caption 1
MN102H75K/F75K/85K/F85K LSI User Manual
VBI control
ON(PCNT0.bp0=0)
ON(PCNT0.bp1=0)
ON(PCNT0.bp0=0)
OFF(PCNT0.bp1=1)
OFF(PCNT0.bp0=1)
OFF(PCNT0.bp1=1)
9.3.2
Clamping Circuit
This block clamps the input video signal (CVBS0, CVBS1).
3.3 V
6.8 k
External
CVBS0, 1
Vidio in
circuit
33 k
The clamping circuit internal to the MN102H75K/85K provides three current
sources—high, medium, and low. You can modify these current sources using
external resistors R1 and R2. Within the clamping circuit, you can turn each of the
current sources on and off in steps. The control bits for these currents are the same
for sync tip and pedestal clamping, but the reference and compare levels are dif-
ferent. Table 9-3 provides these values for the two types of clamping, and table 9-4
shows how to control the three current levels so that the video signal matches the
reference level.
Table 9-3 Clamping Reference and Compare Levels
Reference Level
Clamping
Type
CCD0
Sync tip
16 (dec)
clamping
Pedestal
Value in
clamping
PCLV,
x'007ECC'
229
Panasonic
ADC control
ON(PCNT0.bp4=1)
ON(PCNT0.bp5=1)
ON(PCNT0.bp4=1)
OFF(PCNT0.bp5=0)
OFF(PCNT0.bp4=0)
OFF(PCNT0.bp5=0)
1
CLL
3
5
Clamping
Circuit
A/D
2
CLH
4
6
Figure 9-5 Clamping Circuit
Compare Level
CCD1
CCD0
16 (dec)
Output from minimum
detection circuit (value
in SYNCMIN,
x'007EC8', bits 6-0)
Value in
Value in SYNCMIN,
PCLVW,
x'007EC8', bits 14-8
x'007EEC'
Panasonic Semiconductor Development Company
Clamp control
(P3MD.bp3,2,1)=(0,1,1)
(P3MD.bp3,2,1)=(1,0,1)
(P3MD.bp3,2,1)=(0,0,0)
Control circuit
Data slice
circuit
Sync separator
CCD1
Output from minimum
detection circuit (value
in SYNCMINW,
x'007EE8', bits 6-0)
Value in SYNCMINW,
x'007EE8', bits 14-8
Advertisement
Table of Contents
