Panasonic MN10285K User Manual page 70

Interrupts
Interrupt Control Registers
MN102H75K/F75K/85K/F85K LSI User Manual
OSDCICL: OSD (Text) Interrupt Control Register (Low)
Bit: 7 6 5 4
OSDC
— — —
IR
Reset: 0 0 0 0
R/W: R R R R/W
OSDCICL detects and requests OSD (text) interrupts. It is an 8-bit access
register. Use the MOVB instruction to access it.
OSDCIR: OSD (text) interrupt request flag
0: No interrupt requested
1: Interrupt requested
OSDCID: OSD (text) interrupt detect flag
0: Interrupt undetected
1: Interrupt detected
OSDCICH: OSD (Text) Interrupt Control Register (High)
Bit: 7 6 5 4
— — — —
Reset: 0 0 0 0
R/W: R R R R
OSDCICH enables timer OSD (text) interrupts. It is an 8-bit access register.
Use the MOVB instruction to access it.
The priority level for OSD (text) interrupts is written to the OSDGLV[2:0]
field of the OSDGICH register.
OSDCIE: OSD (text) interrupt enable flag
0: Disable
1: Enable
SCT1ICL: Serial 1 Transmission End Interrupt Control Register (Low) x'00FC98'
Bit: 7 6 5 4
SCT1
— — —
IR
Reset: 0 0 0 0
R/W: R R R R/W
SCT1ICL detects and requests serial 1 transmission end interrupts. It is an
8-bit access register. Use the MOVB instruction to access it.
SCT1IR: Serial 1 transmission end interrupt request flag
0: No interrupt requested
1: Interrupt requested
SCT1ID: Serial 1 transmission end interrupt detect flag
0: Interrupt undetected
1: Interrupt detected
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Panasonic
3 2 1 0
OSDC
— — —
ID
0 0 0 0
R R R R
3 2 1 0
OSDC
— — —
IE
0 0 0 0
R R R R/W
3 2 1 0
SCT1
— — —
ID
0 0 0 0
R R R R
Panasonic Semiconductor Development Company
x'00FC92'
x'00FC93'