Panasonic MN10285K User Manual page 63

Panasonic Semiconductor Development Company
ADM3ICH: Address 3 Match Interrupt Control Register (High)
Bit: 7 6 5 4
ADM3 ADM3 ADM3
—
LV2 LV1 LV0
Reset: 0 0 0 0
R/W: R R/W R/W R/W
ADM3ICH sets the priority level for and enables address match 3 inter-
rupts. It is an 8-bit access register. Use the MOVB instruction to access it.
ADM3LV[2:0]: Address match 3 interrupt priority level
Sets the priority from 0 to 6.
ADM3IE: Address match 3 interrupt enable flag
0: Disable
1: Enable
ADM2ICL: Address 2 Match Interrupt Control Register (Low)
Bit: 7 6 5 4
ADM2
— — —
IR
Reset: 0 0 0 0
R/W: R R R R/W
ADM2ICL detects and requests address match 2 interrupts. It is an 8-bit
access register. Use the MOVB instruction to access it.
ADM2IR: Address match 2 interrupt request flag
0: No interrupt requested
1: Interrupt requested
ADM2ID: Address match 2 interrupt detect flag
0: Interrupt undetected
1: Interrupt detected
ADM2ICH: Address 2 Match Interrupt Control Register (High)
Bit: 7 6 5 4
— — — —
Reset: 0 0 0 0
R/W: R R R R
ADM2ICH enables address match 2 interrupts. It is an 8-bit access regis-
ter. Use the MOVB instruction to access it.
The priority level for address match 2 interrupts is written to the
ADM3LV[2:0] field of the ADM3ICH register.
ADM2IE: Address match 2 interrupt enable flag
0: Disable
1: Enable
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Panasonic
Interrupt Control Registers
3 2 1 0
ADM3
— — —
IE
0 0 0 0
R R R R/W
3 2 1 0
ADM2
— — —
ID
0 0 0 0
R R R R
3 2 1 0
ADM2
— — —
IE
0 0 0 0
R R R R/W
MN102H75K/F75K/85K/F85K LSI User Manual
Interrupts
x'00FC79'
x'00FC7A'
x'00FC7B'