Panasonic MN10285K User Manual page 241

Panasonic Semiconductor Development Company
CRIFA: CRI Frequency Width Register A
(CRIFAW
Bit: 15 14 13 12
CRI2 CRI2 CRI2 CRI2 CRI2
FQW7 FQW6 FQW5 FQW4 FQW3
Reset: 0 0 0 0
R/W: R R R R
The CRIFA and CRIFB registers store the CRI cycles from rising edge to
rising edge, for monitoring whether the CRIs were detected correctly dur-
ing this period.
CRI2FQW[7:0]: CRI frequency width 2
This field indicates the width, in clock units, from the second to the third
rising edge after the CRI.
CRI1FQW[7:0]: CRI frequency width 1
This field indicates the width, in clock units, from the first to the second
rising edge after the CRI.
CRIFB: CRI Frequency Width Register B
(CRIFBW
Bit: 15 14 13 12
CRI4 CRI4 CRI4 CRI4 CRI4
FQW7 FQW6 FQW5 FQW4 FQW3
Reset: 0 0 0 0
R/W: R R R R
CRI4FQW[7:0]: CRI frequency width 4
This field indicates the width, in clock units, from the fourth to the fifth ris-
ing edge after the CRI.
CRI3FQW[7:0]: CRI frequency width 3
This field indicates the width, in clock units, from the third to the fourth
rising edge after the CRI.
CRI1S: CRI Capture Start Timing Control Register 1
(CRI1SW
Bit: 15 14 13 12
— — — —
Reset: 0 0 0 0
R/W: R R R R
CRI1S[10:0]: Start position for CRI capture 1
Valid range: x'000' to x'7FF'
240
Panasonic
Closed-Caption Decoder
Closed-Caption Decoder Registers
11 10 9 8 7 6
CRI2 CRI2 CRI2 CRI1 CRI1
FQW2 FQW1 FQW0 FQW7 FQW6
0 0 0 0 0 0
R R R R R R
11 10 9 8 7 6
CRI4 CRI4 CRI4 CRI3 CRI3
FQW2 FQW1 FQW0 FQW7 FQW6
0 0 0 0 0 0
R R R R R R
11 10 9 8 7 6
CRI1S CRI1S CRI1S CRI1S CRI1S
—
10 9 8 7 6
0 1 1 1 1 1
R R/W R/W R/W R/W R/W
MN102H75K/F75K/85K/F85K LSI User Manual
x'007E0C'
x'007E2C')
5 4 3 2 1
CRI1 CRI1 CRI1 CRI1 CRI1 CRI1
FQW5 FQW4 FQW3 FQW2 FQW1 FQW0
0 0 0 0 0
R R R R R
x'007E0E'
x'007E2E')
5 4 3 2 1
CRI3 CRI3 CRI3 CRI3 CRI3 CRI3
FQW5 FQW4 FQW3 FQW2 FQW1 FQW0
0 0 0 0 0
R R R R R
x'007E10'
x'007E30')
5 4 3 2 1
CRI1S CRI1S CRI1S CRI1S CRI1S CRI1S
5 4 3 2 1
1 1 1 1 1
R/W R/W R/W R/W R/W R/W
0
0
R
0
0
R
0
0
1