Panasonic MN10285K User Manual page 293

Panasonic Semiconductor Development Company
AMCHIH0–AMCHIHF: ROM Correction Address Match Register n (High)
Bit: 7 6 5 4
CHAD CHAD CHAD CHAD
23 22 21 20
Reset: 0 0 0 0
R/W: R/W R/W R/W R/W
AMCHIHn is an 8-bit access register.
CHAD[23:16]: Correction address bits A23 to A16 (A23 = MSB)
AMCHIL0–AMCHILF: ROM Correction Address Match Register n (Low)
Bit: 15 14 13 12
CHAD CHAD CHAD CHAD CHAD
15 14 13 12
Reset: 0 0 0 0
R/W: R/W R/W R/W R/W R/W
AMCHILn is a 16-bit access register.
CHAD[15:0]: Correction address bits A15 to A0
CHDAT0–CHDAT15: ROM Correction Data Register n
Bit: 7 6 5 4
CHD CHD CHD CHD
7 6 5 4
Reset: 0 0 0 0
R/W: R/W R/W R/W R/W
CHDATn is an 8-bit access register.
CHD7: Correction data bit D15 or D7 for address n
CHD6: Correction data bit D14 or D6 for address n
CHD5: Correction data bit D13 or D5 for address n
CHD4: Correction data bit D112 or D4 for address n
CHD3: Correction data bit D11 or D3 for address n
CHD2: Correction data bit D10 or D2 for address n
CHD1: Correction data bit D9 or D1 for address n
CHD0: Correction data bit D8 or D0 for address n
292
Panasonic
ROM Correction Control Registers
3 2 1 0
CHAD CHAD CHAD CHAD
19 18 17 16
0 0 0 0
R/W R/W R/W R/W
11 10 9 8 7 6
CHAD CHAD CHAD CHAD CHAD
11 10 9 8 7 6
0 0 0 0 0 0
R/W R/W R/W R/W R/W
3 2 1 0
CHD CHD CHD CHD
3 2 1 0
0 0 0 0
R/W R/W R/W R/W
MN102H75K/F75K/85K/F85K LSI User Manual
ROM Correction
5 4 3 2 1
CHAD CHAD CHAD CHAD CHAD CHAD
5 4 3 2 1
0 0 0 0 0
R/W R/W R/W R/W R/W R/W
0
0
0