Table of Contents
Advertisement
Timers
8-Bit Timer Setup Examples
Do not change the clock source
once you select it. Selecting the
clock source while you set up
the count operation control will
corrupt the value in the binary
counter.
In the bank and linear address-
ing versions of the MN102
series, it was necessary to set
TM0EN and TM0LD to 0
between steps 5 and 6, to
ensure stable operation. This is
unnecessary in the high-speed
linear addressing version.
MN102H75K/F75K/85K/F85K LSI User Manual
TM0UDICL (example)
Bit:
7
6
5
4
TM0UD
—
—
—
IR
Setting:
0
0
0
0
TM0UDICH (example)
Bit:
7
6
5
4
—
—
—
—
Setting:
0
0
0
0
4.
Set the divide-by ratio for timer 0. Since the timer will count 4 TM0IO
cycles, write x'03' to the timer 0 base register (TM0BR). (The valid range
for TM0BR is 0 to 255.)
TM0BR (example)
Bit:
7
6
5
4
TM0
TM0
TM0
TM0
BR7
BR6
BR5
BR4
Setting:
0
0
0
0
5.
Set the TM0LD bit of the TM0MD register to 1. This loads the value in the
base register to the binary counter. At the same time, select the clock source
as the TM0IO signal input by writing b'11' to TM0S[1:0].
TM0MD (example)
Bit:
7
6
5
4
TM0
TM0
—
—
EN
LD
Setting:
0
1
0
0
6.
Set TM0LD to 0 and TM0EN to 1. This starts the timer. Counting begins at
the start of the next cycle. When the binary counter reaches 0 and loads the
value x'03' from the base register, in preparation for the next count, a timer 0
underflow interrupt request is sent to the CPU.
Interrupt enable
TM0BR
TM0BC
Timer 0 underflow
interrupt
TM0IO
Sequence
Figure 4-10 Event Counter Timing (Timer 0)
83
Panasonic
3
2
1
0
TM0UD
—
—
—
ID
0
0
0
0
3
2
1
0
TM0UD
—
—
—
IE
0
0
0
1
3
2
1
0
TM0
TM0
TM0
TM0
BR3
BR2
BR1
BR0
0
0
1
1
3
2
1
0
TM0
TM0
—
—
S1
S0
0
0
1
1
00
00
(2)
(3)
(5)
TM0UDICH(B)
TM0MD(B)
(4)
TM0BR(B)
Panasonic Semiconductor Development Company
x'00FC74'
x'00FC75'
x'00FE10'
x'00FE20'
03
03
02
01
00
03
(6)
TM0MD(B)
Advertisement
Table of Contents
