Event Counter Timing (Timer 4); Panasonic - Panasonic MN10285K User Manual

Timers
16-Bit Timer Setup Examples
MN102H75K/F75K/85K/F85K LSI User Manual
TM4CA (example)
Bit: 15 14 13 12
TM4 TM4 TM4 TM4 TM4
CA15 CA14 CA13 CA12 CA11
Setting: 0 0 0 0
3. Set the phase difference for timer 4. For a 2-cycle phase difference, write
x'0001' to timer 4 compare/capture register B (TM4CB). (The valid range is
-1 TM4CB the TM4CA value.)
TM4CB (example)
Bit: 15 14 13 12
TM4 TM4 TM4 TM4 TM4
CB15 CB14 CB13 CB12 CB11
Setting: 0 0 0 0
4. Set the TM4NLD bit of the TM4MD register to 1 and the TM4EN bit to 0.
This enables TM4BC and the S-R flip-flop. This step ensures stable opera-
tion. If it is omitted, the binary counter may not count the first cycle. Do not
change any other operating modes during this step.
5. Set TM4NLD and TM4EN to 1. This starts the timer. Counting begins at the
start of the next cycle.
To enable timer 4 capture interrupts:
Cancel all existing interrupt requests. Next, set the interrupt priority level in the
TM4CBLV[2:0] bits of the TM4CBICH register (levels 0 to 6), set the TM4CBIE
bit to 1, set the TM4CBIR bit of TM4CBICL to 0, set the TM4CAIE bit of
TM4CAICH to 1, and set the TM4CAIR bit of TM4CAICL to 0. From this point
on, an interrupt request is generated whenever a timer 4 capture A or capture B
event occurs.
Timer 4 can operate as an event counter, but timer 4 does not operate in STOP
mode, when B is off. If you use an external clock, it must be synchronized to
OSC
B . This means that the frequency of the event counter clock must be 1/4 or
OSC
less that of the oscillator (6 MHz with a 24-MHz oscillator).
Figure 4-28 shows an example timing chart.
TM4CA
TM4CB
0000
TM4BC
TM4IB
Interrupts
Figure 4-28 Event Counter Timing (Timer 4)
95

Panasonic

11 10 9 8 7 6
TM4 TM4 TM4 TM4 TM4
CA10 CA9 CA8 CA7 CA6
0 0 0 0 0 0
11 10 9 8 7 6
TM4 TM4 TM4 TM4 TM4
CB10 CB9 CB8 CB7 CB6
0 0 0 0 0 0
0004
0001
0001 0002 0003 0004
B
Panasonic Semiconductor Development Company
x'00FE84'
5 4 3 2 1
TM4 TM4 TM4 TM4 TM4
CA5 CA4 CA3 CA2 CA1
0 0 0 1 0
x'00FE88'
5 4 3 2 1
TM4 TM4 TM4 TM4 TM4
CB5 CB4 CB3 CB2 CB1
0 0 0 0 0
0000 0001 0002 0003 0004
A B
0
TM4
CA0
0
0
TM4
CB0
1
A