Panasonic MN10285K User Manual page 98

Timers
16-Bit Timer Setup Examples
Use the MOV instruction for this
setup and only use 16-bit write
operations.
This step stops the TM4BC
count and clears both TM4BC
and the S-R flip-flop to 0.
MN102H75K/F75K/85K/F85K LSI User Manual
P2DIR (example)
Bit: 7 6 5 4
P2 P2 P2 P2
DIR7 DIR6 DIR5 DIR4
Setting: 0 1 0 0
To set up timer 4:
1. Set the operating mode in the timer 4 mode register (TM4MD). Disable
timer 4 counting and interrupts. Select up counting. Select B
clock source. Select the double-buffer operating mode.
TM4MD (example)
Bit: 15 14 13 12
TM4 TM4 TM4
— —
EN NLD UD1
Setting: 0 0 0 0
2. Set the divide-by ratio for timer 4. To divide B
timer 4 compare/capture register A (TM4CA). (The valid range for TM4CA
is x'0001' to x'FFFE'.)
TM4CA (example)
Bit: 15 14 13 12
TM4 TM4 TM4 TM4 TM4
CA15 CA14 CA13 CA12 CA11
Setting: 0 0 0 0
3. Set the timer 4 duty cycle. For a 2/5 B
timer 4 compare/capture register B (TM4CB). (The valid range is -1
TM4CB the TM4CA value.)
TM4CB (example)
Bit: 15 14 13 12
TM4 TM4 TM4 TM4 TM4
CB15 CB14 CB13 CB12 CB11
Setting: 0 0 0 0
4. Write a dummy data word (of any value) to TM4CAX. In double-buffer
mode, TM4CA is compared to TM4CAX. The contents of TM4CA are
loaded to TM4CAX when TM4BC = TM4CAX. However, since TM4CAX
is undefined or x'0000' before this operation starts, this initial dummy write
prevents timing errors.
5. Write a dummy data word (of any value) to TM4CBX. In double-buffer
mode, TM4CB is compared to TM4CBX. The contents of TM4CB are
loaded to TM4CBX when TM4BC = TM4CBX. However, since TM4CBX
is undefined or x'0000' before this operation starts, this initial dummy write
prevents timing errors.
97
Panasonic
3 2 1 0
P2 P2 P2 P2
DIR3 DIR2 DIR1 DIR0
0 0 0 0
11 10 9 8 7 6
TM4 TM4 TM4 TM4 TM4
UD0 TGE ONE MD1 MD0
0 0 0 0 0 1
11 10 9 8 7 6
TM4 TM4 TM4 TM4 TM4
CA10 CA9 CA8 CA7 CA6
0 0 0 0 0 0
/4 duty cycle, write x'0001' to
OSC
11 10 9 8 7 6
TM4 TM4 TM4 TM4 TM4
CB10 CB9 CB8 CB7 CB6
0 0 0 0 0 0
Panasonic Semiconductor Development Company
x'00FFE2'
/4 as the
OSC
x'00FE80'
5 4 3 2 1
TM4 TM4 TM4 TM4 TM4 TM4
ECLR LP ASEL S2 S1
0 1 0 0 1
/4 by 5, write x'0004' to
OSC
x'00FE84'
5 4 3 2 1
TM4 TM4 TM4 TM4 TM4 TM4
CA5 CA4 CA3 CA2 CA1 CA0
0 0 0 1 0
x'00FE88'
5 4 3 2 1
TM4 TM4 TM4 TM4 TM4 TM4
CB5 CB4 CB3 CB2 CB1 CB0
0 0 0 0 0
0
S0
1
0
0
0
1