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Panasonic Semiconductor Development Company
1.7.2
Bus Interface Control Registers
The external memory wait register (EXWMD) and memory mode register 1
(MEMMD1) control the bus interface.
EXWMD: External Memory Wait Register
Bi t : 15
14
13
12
EW 33 EW 32 EW 31 EW 30 EW 23 EW 22 EW 21 EW 20 EW 13 EW 12 EW 11 EW 10 EW 03 EW 02 EW 01 EW 00
Res et :
1
1
1
0
R/ W : R/ W
R/ W
R/ W
R/ W
R/ W
EW[33:30], EW[23:20], EW[13:10], EW[03:00]
These fields contain the wait settings for external memory spaces 3, 2, 1,
and 0, respectively. One wait corresponds to one instruction cycle. When
the external oscillator is 4 MHz, one wait is 83 ns.
The OSD, VBI0, VBI1, I2C, IR remote signal receiver, and H counter
blocks apply to external memory space 0.
Table 1-4 Wait Count Settings
EW[n3:n0] Setting
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
MEMMD1: Memory Mode Register 1
Bi t : 15
14
13
12
EB31 EB32 EB21 EB20 EB11 EB10 EB01 EB00 BRS1 BRS0 BRC3 BRC2 BRC1 BRC0 I O W 1 I O W 0
Res et :
0
0
0
0
R/ W : R/ W
R/ W
R/ W
R/ W
R/ W
Write 0s to bits 15 to 2.
IOW[1:0]: Wait setting for internal I/O space
00: 1 wait
01: Reserved
10: 2 waits
11: 3 waits
36
Panasonic
11
10
9
8
7
6
1
1
1
0
1
1
R/ W
R/ W
R/ W
R/ W
R/ W
Wait Count
0. 0
Res er ved
1. 0
Res er ved
2. 0
Res er ved
3. 0
Res er ved
4. 0
Res er ved
5. 0
Res er ved
6. 0
Res er ved
7. 0
Res er ved
11
10
9
8
7
6
0
0
0
0
0
0
R/ W
R/ W
R/ W
R/ W
R/ W
MN102H75K/F75K/85K/F85K LSI User Manual
General Description
Bus Interface
x'00FF80'
5
4
3
2
1
0
1
0
1
1
1
0
R/ W
R/ W
R/ W
R/ W
R/ W
R/ W
Cycles
1. 0
2. 0
3. 0
4. 0
5. 0
6. 0
7. 0
8. 0
x'00FF82'
5
4
3
2
1
0
0
0
0
0
1
1
R/ W
R/ W
R/ W
R/ W
R/ W
R/ W
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