Setting Up A Two-Phase Pwm Output Signal Using Timer 4; Block Diagram Of Two-Phase Pwm Output Using Timer 4; Panasonic - Panasonic MN10285K User Manual

Timers
16-Bit Timer Setup Examples
MN102H75K/F75K/85K/F85K LSI User Manual
4.11.3 Setting Up a Two-Phase PWM Output Signal Using
Timer 4
In this example, timer 4 is used to divide timer 0 underflow by 5 and generate a
five-cycle, two-phase PWM signal. The phase difference of this signal is 2
cycles. To accomplish this, the program must load the divide-by ratio of 5 (actual
setting: 4) into compare/capture register A and a cycle count of 2 (actual setting:
1) into compare/capture register B.
P3
P6
TM4OA
P2
TM4OB
Timer 4
Timer 0
underflow
up
Figure 4-32 Block Diagram of Two-Phase PWM Output Using Timer 4
To set up the output port:
Set the P2MD[13:12] bits of the port 2 output mode register (P2MD) to b'01'
(selecting the TM4IOA pin), set the P2MD[11:10] bits to b'01' (selecting the
TM4IOB pin), and set the P2DIR[6:5] bits of the port 2 I/O control register
(P2DIR) to b'11' (selecting output direction). This step selects the TM4OA (P26)
and TM4OB (P25) pins as the timer output ports.
P2MD (example)
Bit: 15 14 13 12
P2 P2 P2
—
MD14 MD13 MD12 MD11
Setting: 0 0 0 1
101

Panasonic

CORE
Interrupts
Timers 0-3
Timers 4-5
A. Chip Level
TM4BC
TM4CA
TM4CAX
TM4CB
TM4CBX
B. Block Level
11 10 9 8 7 6
P2 P2 P2 P2 P2 P2
MD10 MD9 MD8 MD7 MD6
0 1 0 0 0 0
Panasonic Semiconductor Development Company
ROM, RAM
P4
Bus Controller
P5
Serial I/Fs
ADC
TM4OA
T Q
R
Q
S
TM4OB
T Q
x'00FFF4'
5 4 3 2 1
P2 P2 P2 P2 P2
MD5 MD4 MD3 MD2 MD1
0 0 0 0 0
0
P2
MD0
0