I 2 C Bus Interface Registers; Sta And Sto Settings - Panasonic MN10285K User Manual

SCL is held low during interrupt
servicing, and is cleared high by
a write to I2CDTRM.
Panasonic Semiconductor Development Company
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13.7 I C Bus Interface Registers
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All registers in I C blook cannot be written by byte (by word only). Read by byte
is possible.
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I2CDTRM: I C Transmission Data Register
Bit: 15 14 13 12
— — — —
Reset: 0 0 0 0
R/W: R R R R
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STA: I C start control
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STO: I C stop control
Writing to the STA and STO bits allows you to change the state of the
transmission or reception operation. Table 13-6 shows the settings for dif-
ferent start and stop conditions.
Table 13-6 STA and STO Settings
STA STO Mode
All
0 0
1 1 All
Slave receiver
1 0
Master transmitter
Slave receiver
0 1
Master transmitter
ACK: Acknowledge signal output control
The acknowledge signal is output after every byte transfer, on the ninth
clock pulse. ACK is normally 1 and transitions to 0 to output an acknowl-
edge (for instance if the master or slave receiver has received a data byte).
DT[7:0]: Data to be transmitted
The parallel data in this field is converted to serial data for transmission to
2
the I C bus. It is shifted out MSB first to the interface.
304
Panasonic
11 10 9 8 7 6
— STA STO ACK DT7 DT6
0 0 0 0 0 0
R R/W R/W R/W R/W R/W
Function
NOP No state change
NOP No state change
Start Change to mode indicated by R/W bit.
Repeat start R/W = 0: Change to master transmitter
R/W = 1: Change to master receiver
Stop read Change to slave receiver after stop
Stop write condition.
MN102H75K/F75K/85K/F85K LSI User Manual
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I C Bus Controller
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I C Bus Interface Registers
x'007E40'
5 4 3 2 1 0
DT5 DT4 DT3 DT2 DT1 DT0
0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W
Description