Pxpepbar-Pci Express Egress Port Base Address Register - Intel 2ND GENERATION CORE PROCESSOR FAMILY DESKTOP - DATASHEET VOLUME 2 01-2011 Datasheet

Processor Configuration Registers
2.5.10 PXPEPBAR—PCI Express Egress Port Base Address
Register
This is the base address for the PCI Express Egress Port MMIO Configuration space.
There is no physical memory within this 4 KB window that can be addressed. The 4 KB
reserved by this register does not alias to any PCI 2.3 compliant memory mapped
space. On reset, the EGRESS port MMIO configuration space is disabled and must be
enabled by writing a 1 to PXPEPBAREN [Device 0, offset 40h, bit 0].
All the bits in this register are locked in Intel TXT mode.
B/D/F/Type:
Address Offset:
Reset Value:
Access:
Size:
BIOS Optimal Default
Bit
63:39
38:12
11:1
0
Datasheet, Volume 2
0/0/0/PCI
40–47h
0000000000000000h
RW
64 bits
000000000h
Reset RST/
Attr
Value PWR
RO 0h
RW 0000000h Uncore
RO 0h
RW 0b Uncore
Description
Reserved
PCI Express Egress Port MMIO Base Address (PXPEPBAR)
This field corresponds to bits 38:12 of the base address PCI
Express Egress Port MMIO configuration space. BIOS will program
this register resulting in a base address for a 4 KB block of
contiguous memory address space. This register ensures that a
naturally aligned 4 KB space is allocated within the first 512 GB of
addressable memory space. System Software uses this base
address to program the PCI Express Egress Port MMIO register set.
All the bits in this register are locked in Intel TXT mode.
Reserved
PXPEPBAR Enable (PXPEPBAREN)
0 = Disabled. PXPEPBAR is disabled and does not claim any
memory
1 = Enabled. PXPEPBAR memory mapped accesses are claimed
and decoded appropriately
This register is locked by Intel TXT.
55