Mitsubishi Electric MELSEC iQ-F FX5 Series User Manual page 35

Output data hold/clear operation during CPU STOP
The following figure shows the devices where the setting of "Output Hold/Clear Setting during CPU STOP" is enabled when
the CPU module on the sending side changes from RUN to STOP.
■At unicast mode
No.0
RX
No.1
No.2
No.3
RY
No.1
No.2
No.3
RWr
No.1
No.2
No.3
RWw
No.1
No.2
No.3
: When the link refresh source is set to a source other than Y, data is held or cleared according to the parameter setting. When the link refresh source is set
to Y, data is cleared regardless of the parameter setting.
: Data is held regardless of the parameter setting.
No.1
RWr
No.1
RWw
No.1
No.2
RWr
No.2
RWw
No.2
3.2 Cyclic Transmission
3
No.3
RX
No.3
RY
No.3
RWr
No.3
RWw
No.3
3 FUNCTIONS
33