Mitel SX-200 Practices page 1161

m .
DATASR
1100
Series Description
Circuit Description
14.7
The microprocessor controls the operations within the dataset. It adds High-level
Data Link Control (HDLC) control bytes to incoming data received through its
W-232 port, before the data is passed to the HDLC Controller to be packetized and
sent out via the DNIC to the PABX. Similarly data received through the PABX has its
address and HDLC control bytes stripped off before it is sent out on the W-232 port.
Once a call is established by the use of D-channel signals to the PABX, data
communication occurs on the B-channel, and passes straight through the PABX to
its destination. Figure 14-5 is a block diagram of the DATASET I 100 series.
The LEDs and keys, which interface the DATASET I 100 series to the user, connect to
the microprocessor,
The external random access memory (HAM) provides buffering for error correction and
speed conversion, as well as improving flow control through the DATASET I 100 series.
Error correction is by retransmitting frames in which errors had been detected.
The HDLC controller is a single channel interface between the microprocessor and the
DNlC/AW& control signals are sent on the D-channel, while data is sent on the
B2-channel. Each section of the DATASET I 102 Dual Rack Mounted card has its own
B-channel, but shares the D-channel for control,
FE+232
INTERFACE
Figure 14-S Typical DATASET 1100 Series Block Diagram
9109-096-126-NA
Issue1
Revision
0 126 14-11