Vcu118 Board User And Mgt Clocks - Xilinx VCU118 User Manual

The U104 clock MUX input select pin 2 is wired to 2-pin header J9 and a pull-down resistor.
The default J9 setting is jumper OFF, which allows the pull-down resistor to select U104
input CLK0, the SI570 U32. The SI5335A quad clock generator U122 CLK1 300 MHz fixed
frequency output, wired to U104 input CLK1, is selected as the U104 source clock when a
jumper block is installed on J9, pulling the U104 select signal High and selecting the U104
CLK1 input.
On power-up, the U32 SI570 user clock defaults to an output frequency of 156.250 MHz.
The system controller and user applications can change the output frequency within the
range of 10 MHz to 810 MHz through an I
board resets the user clock to the default frequency of 156.250 MHz.
• Programmable oscillator: Silicon Labs Si570BAB0000544DG (10 MHz-810 MHz)
• Frequency tolerance: 50 ppm
• 3.3V LVDS differential output
The I²C programmable SI570 U32/SI53340 U104 clock buffer circuit is shown in
X-Ref Target - Figure 3-5
VCU118 Board User Guide
UG1224 (v1.0) December 15, 2016
Figure 3-5: VCU118 Board User and MGT Clocks
www.xilinx.com
Chapter 3: Board Component Descriptions
2
C interface. Power cycling the VCU118 evaluation
Figure 3-5.
X18003-100416
46
Send Feedback