Programmable Mgt User Clock - Xilinx KCU116 User Manual

Programmable MGT User Clock

[Figure 2-1, callout 7]
The KCU116 evaluation board has a SI570 programmable low-jitter 3.3V LVDS differential
oscillator (U56) connected (series capacitor AC coupled) to the FPGA U1 MGTY226
MGTREFCLK1 P/N inputs (pin M7 (P) and M6 (N)).
On power-up, the SI570 user clock defaults to an output frequency of 156.250 MHz. User
applications or the system controller can change the output frequency within the range of
10 MHz to 810 MHz through an I
resets the user clock to the default frequency of 156.250 MHz. The system controller can be
configured to reprogram the Si570 U56 to a saved frequency immediately after board
power-up.
• Programmable oscillator: Silicon Labs Si570BAB0000544DG (10 MHz-810 MHz)
• Frequency jitter: 50 ppm
• 3.3V LVDS differential output
The user MGT clock circuit is shown in
X-Ref Target - Figure 3-7
KCU116 Board User Guide
UG1239 (v1.2) September 28, 2018
2
C interface. Power cycling the KCU116 evaluation board
Figure
Figure 3‐7: KCU116 Board User Clocks
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Chapter 3: Board Component Descriptions
3-7.
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